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                             24 results found
no title author magazine year volume issue page(s) type
1 Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain Najmzadeh, M.
2012
74 C p. 114-120
7 p.
article
2 ALD high-k layer grating couplers for single and double slot on-chip SOI photonics Naiini, Maziar M.
2012
74 C p. 58-63
6 p.
article
3 AlGaN/GaN power amplifiers for ISM applications Krausse, D.
2012
74 C p. 108-113
6 p.
article
4 CMOS compatible self-aligned S/D regions for implant-free InGaAs MOSFETs Czornomaz, L.
2012
74 C p. 71-76
6 p.
article
5 Comparative study of circuit perspectives for multi-gate structures at sub-10nm node Lacord, J.
2012
74 C p. 25-31
7 p.
article
6 Compensation of externally applied mechanical stress by stacking of ultrathin chips Endler, Stefan
2012
74 C p. 102-107
6 p.
article
7 Comprehensive investigation of the impact of lateral charge migration on retention performance of planar and 3D SONOS devices Maconi, A.
2012
74 C p. 64-70
7 p.
article
8 Editorial Board 2012
74 C p. IFC-
1 p.
article
9 Enhancement of FinFET performance using 25-nm-thin sidewall spacer grown by atomic layer deposition Endo, Kazuhiko
2012
74 C p. 13-18
6 p.
article
10 Experimental study of electron mobility characterization in direct contact La-silicate/Si structure based nMOSFETs Kawanago, T.
2012
74 C p. 2-6
5 p.
article
11 Foreword Östling, Mikael
2012
74 C p. 1-
1 p.
article
12 Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks Henkel, Christoph
2012
74 C p. 7-12
6 p.
article
13 Nanoscale carrier injectors for high luminescence Si-based LEDs Piccolo, G.
2012
74 C p. 43-48
6 p.
article
14 On the efficiency of stress techniques in gate-last n-type bulk FinFETs Eneman, Geert
2012
74 C p. 19-24
6 p.
article
15 Parasitic bipolar impact in 32nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology Fenouillet-Beranger, C.
2012
74 C p. 32-37
6 p.
article
16 PNP PIN bipolar phototransistors for high-speed applications built in a 180nm CMOS process Kostov, P.
2012
74 C p. 49-57
9 p.
article
17 PureGaB p+n Ge diodes grown in large windows to Si with a sub-300nm transition region Sammak, Amir
2012
74 C p. 126-133
8 p.
article
18 Study on dual-lateral-gate suspended-body single-walled carbon nanotube field-effect transistors Cao, Ji
2012
74 C p. 121-125
5 p.
article
19 The electron–hole bilayer tunnel FET Lattanzio, Livio
2012
74 C p. 85-90
6 p.
article
20 Transient electro-thermal characterization of Si–Ge heterojunction bipolar transistors Sahoo, Amit Kumar
2012
74 C p. 77-84
8 p.
article
21 Tunneling field-effect transistor with a strained Si channel and a Si0.5Ge0.5 source Zhao, Q.T.
2012
74 C p. 97-101
5 p.
article
22 Two-stage trigger silicon-controller rectifier (SCR) for radio-frequency (RF) input and output protections in nanometer technologies Lee, Jian-Hsing
2012
74 C p. 134-141
8 p.
article
23 Understanding device performance by incorporating 2D-carrier profiles from high resolution scanning spreading resistance microscopy into device simulations Nazir, Aftab
2012
74 C p. 38-42
5 p.
article
24 Virtually dopant-free CMOS: Midgap Schottky-barrier nanowire field-effect-transistors for high temperature applications Wessely, F.
2012
74 C p. 91-96
6 p.
article
                             24 results found
 
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