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                             31 results found
no title author magazine year volume issue page(s) type
1 An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models Pereira, A.S.N.
 2017
 128 C p. 67-71
5 p.
 article
2 Anisotropic interpolation method of silicon carbide oxidation growth rates for three-dimensional simulation Šimonka, Vito
 2017
 128 C p. 135-140
6 p.
 article
3 Back-gated InGaAs-on-insulator lateral N+NN+ MOSFET: Fabrication and typical conduction mechanisms Park, H.J.
 2017
 128 C p. 80-86
7 p.
 article
4 Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits Strangio, S.
 2017
 128 C p. 37-42
6 p.
 article
5 Characterization and modelling of layout effects in SiGe channel pMOSFETs from 14nm UTBB FDSOI technology Berthelon, R.
 2017
 128 C p. 72-79
8 p.
 article
6 Confinement orientation effects in S/D tunneling Medina-Bailon, C.
 2017
 128 C p. 48-53
6 p.
 article
7 DC and RF characterization of InGaAs replacement metal gate (RMG) nFETs on SiGe-OI FinFETs fabricated by 3D monolithic integration Deshpande, V.
 2017
 128 C p. 87-91
5 p.
 article
8 Drain current local variability from linear to saturation region in 28nm bulk NMOSFETs Karatsori, T.A.
 2017
 128 C p. 31-36
6 p.
 article
9 Editorial Board 2017
 128 C p. IFC-
1 p.
 article
10 Electrical characterization and modeling of 1T-1R RRAM arrays with amorphous and poly-crystalline HfO2 Grossi, Alessandro
 2017
 128 C p. 187-193
7 p.
 article
11 Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements Tomaszewski, Daniel
 2017
 128 C p. 92-101
10 p.
 article
12 Framework to model neutral particle flux in convex high aspect ratio structures using one-dimensional radiosity Manstetten, Paul
 2017
 128 C p. 141-147
7 p.
 article
13 Inverse-magnetostriction-induced switching current reduction of STT-MTJs and its application for low-voltage MRAM Takamura, Yota
 2017
 128 C p. 194-199
6 p.
 article
14 Low frequency noise assessment in n- and p-channel sub-10nm triple-gate FinFETs: Part II: Measurements and results Boudier, D.
 2017
 128 C p. 109-114
6 p.
 article
15 Low frequency noise assessment in n- and p-channel sub-10nm triple-gate FinFETs: Part I: Theory and methodology Boudier, D.
 2017
 128 C p. 102-108
7 p.
 article
16 Numerical investigation of plasma effects in silicon MOSFETs for THz-wave detection Jungemann, C.
 2017
 128 C p. 129-134
6 p.
 article
17 Process modules for GeSn nanoelectronics with high Sn-contents Schulte-Braucks, C.
 2017
 128 C p. 54-59
6 p.
 article
18 Reconfigurable field effect transistor for advanced CMOS: Advantages and limitations Navarro, C.
 2017
 128 C p. 155-162
8 p.
 article
19 Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28nm FD-SOI technology Athanasiou, Sotirios
 2017
 128 C p. 172-179
8 p.
 article
20 Reliable gate stack and substrate parameter extraction based on C-V measurements for 14nm node FDSOI technology Mohamad, B.
 2017
 128 C p. 10-16
7 p.
 article
21 RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers Kazemi Esfeh, B.
 2017
 128 C p. 121-128
8 p.
 article
22 Scaling/LER study of Si GAA nanowire FET using 3D finite element Monte Carlo simulations Elmessary, Muhammad A.
 2017
 128 C p. 17-24
8 p.
 article
23 Sharp-switching band-modulation back-gated devices in advanced FDSOI technology El Dirani, Hassan
 2017
 128 C p. 180-186
7 p.
 article
24 Simulation study of a novel 3D SPAD pixel in an advanced FD-SOI technology Vignetti, M.M.
 2017
 128 C p. 163-171
9 p.
 article
25 SOI technology for power management in automotive and industrial applications Stork, Johannes M.C.
 2017
 128 C p. 3-9
7 p.
 article
26 Special Issue of Solid-State Electronics, dedicated to EUROSOI-ULIS 2016 Sverdlov, Viktor
 2017
 128 C p. 1-2
2 p.
 article
27 Study of line-TFET analog performance comparing with other TFET and MOSFET architectures Agopian, Paula Ghedini Der
 2017
 128 C p. 43-47
5 p.
 article
28 Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K Paz, Bruna Cardoso
 2017
 128 C p. 60-66
7 p.
 article
29 Systematic method for electrical characterization of random telegraph noise in MOSFETs Marquez, Carlos
 2017
 128 C p. 115-120
6 p.
 article
30 Tuning the tunneling probability by mechanical stress in Schottky barrier based reconfigurable nanowire transistors Baldauf, Tim
 2017
 128 C p. 148-154
7 p.
 article
31 Variability and self-average of impurity-limited resistance in quasi-one dimensional nanowires Sano, Nobuyuki
 2017
 128 C p. 25-30
6 p.
 article
                             31 results found
 
 Koninklijke Bibliotheek - National Library of the Netherlands