| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits
|
Higami, Yoshinobu
|
|
2000
|
16 |
5 |
p. 443-451
|
artikel
|
| 2 |
A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency
|
Ohtake, Satoshi
|
|
2000
|
16 |
5 |
p. 553-566
|
artikel
|
| 3 |
A Practical Vector Restoration Technique for Large Sequential Circuits
|
Bommu, Surendra K.
|
|
2000
|
16 |
5 |
p. 521-539
|
artikel
|
| 4 |
BIST TPG for Combinational Cluster Interconnect Testing at Board Level
|
Chiang, Chen-Huan
|
|
2000
|
16 |
5 |
p. 427-442
|
artikel
|
| 5 |
Dynamic Power Supply Current Testing of CMOS SRAMs
|
Liu, Jian
|
|
2000
|
16 |
5 |
p. 499-511
|
artikel
|
| 6 |
Editorial
|
Agrawal, Vishwani D.
|
|
2000
|
16 |
5 |
p. 403-404
|
artikel
|
| 7 |
False-Path Removal Using Delay Fault Simulation
|
Gharaybeh, Marwan A.
|
|
2000
|
16 |
5 |
p. 463-476
|
artikel
|
| 8 |
Guest Editorial
|
Demidenko, Serge
|
|
2000
|
16 |
5 |
p. 407-408
|
artikel
|
| 9 |
IDDQ Testing of Submicron CMOS—by Cooling?
|
Rencz, M.
|
|
2000
|
16 |
5 |
p. 453-461
|
artikel
|
| 10 |
LFSR-Based Deterministic TPG for Two-Pattern Testing
|
Li, Xiaowei
|
|
2000
|
16 |
5 |
p. 419-426
|
artikel
|
| 11 |
Reduction of Number of Paths to be Tested in Delay Testing
|
Li, Huawei
|
|
2000
|
16 |
5 |
p. 477-485
|
artikel
|
| 12 |
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
|
Pomeranz, Irith
|
|
2000
|
16 |
5 |
p. 541-552
|
artikel
|
| 13 |
Test Cycle Count Reduction in a Parallel Scan BIST Environment
|
Ayari, Bechir
|
|
2000
|
16 |
5 |
p. 409-418
|
artikel
|
| 14 |
Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy
|
Hamdioui, Said
|
|
2000
|
16 |
5 |
p. 487-498
|
artikel
|
| 15 |
Testing the Local Interconnect Resources of SRAM-Based FPGA's
|
Renovell, M.
|
|
2000
|
16 |
5 |
p. 513-520
|
artikel
|
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