|
Tijdschrift beschrijving
Alle jaargangen van het bijbehorende tijdschrift
Alle afleveringen van het bijbehorende jaargang
Alle artikelen van de bijbehorende aflevering
24 gevonden resultaten
| nr | titel | auteur | tijdschrift | jaar | jaarg. | afl. | pagina('s) | type |
| 1 | A Functional Decomposition Method for Redundancy Identification and Test Generation |
Michael L. Bushnell |
1997 |
10 | 3 |
p. 175-195 21 p. |
artikel |
|
| 2 | A Functional Decomposition Method for Redundancy Identification and Test Generation |
Bushnell, Michael L. |
1997 |
10 | 3 |
p. 175-195 |
artikel |
|
| 3 | Delay Test Generation: A Hardware Perspective |
Jacob Savir |
1997 |
10 | 3 |
p. 245-254 10 p. |
artikel |
|
| 4 | Delay Test Generation: A Hardware Perspective |
Savir, Jacob |
1997 |
10 | 3 |
p. 245-254 |
artikel |
|
| 5 | Editorial |
Vishwani D. Agrawal |
1997 |
10 | 3 |
p. 171-171 1 p. |
artikel |
|
| 6 | Editorial |
Agrawal, Vishwani D. |
1997 |
10 | 3 |
p. 171 |
artikel |
|
| 7 | Exhaustive and Near-Exhaustive Memory Testing Techniques and theirBIST Implementations |
Debaleena Das |
1997 |
10 | 3 |
p. 215-229 15 p. |
artikel |
|
| 8 | Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations |
Das, Debaleena |
1997 |
10 | 3 |
p. 215-229 |
artikel |
|
| 9 | Hierarchical Delay Test Generation |
C.P. Ravikumar |
1997 |
10 | 3 |
p. 231-244 14 p. |
artikel |
|
| 10 | Hierarchical Delay Test Generation |
Ravikumar, C.P. |
1997 |
10 | 3 |
p. 231-244 |
artikel |
|
| 11 | Hierarchical VLSI Fault Tracing by Successive CircuitExtraction from CAD Layout Data in the CAD-Linked EB TestSystem |
Katsuyoshi Miura |
1997 |
10 | 3 |
p. 255-269 15 p. |
artikel |
|
| 12 | Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System |
Miura, Katsuyoshi |
1997 |
10 | 3 |
p. 255-269 |
artikel |
|
| 13 | List of Reviewers |
1997 |
10 | 3 |
p. 174-174 1 p. |
artikel |
||
| 14 | List of Reviewers |
1997 |
10 | 3 |
p. 174 |
artikel |
||
| 15 | Module Level Weighted Random Patterns |
Jacob Savir |
1997 |
10 | 3 |
p. 283-287 5 p. |
artikel |
|
| 16 | Module Level Weighted Random Patterns |
Savir, Jacob |
1997 |
10 | 3 |
p. 283-287 |
artikel |
|
| 17 | New Editorial Board Members |
1997 |
10 | 3 |
p. 173-173 1 p. |
artikel |
||
| 18 | New Editorial Board Members |
1997 |
10 | 3 |
p. 173 |
artikel |
||
| 19 | Symbolic Handling of Bridging Fault Effects |
Michele Favalli |
1997 |
10 | 3 |
p. 271-276 6 p. |
artikel |
|
| 20 | Symbolic Handling of Bridging Fault Effects |
Favalli, Michele |
1997 |
10 | 3 |
p. 271-276 |
artikel |
|
| 21 | Testing for Bounded Faults in RAMs |
R. David |
1997 |
10 | 3 |
p. 197-214 18 p. |
artikel |
|
| 22 | Testing for Bounded Faults in RAMs |
David, R. |
1997 |
10 | 3 |
p. 197-214 |
artikel |
|
| 23 | Workload Distribution in Fault Simulation |
Minesh B. Amin |
1997 |
10 | 3 |
p. 277-282 6 p. |
artikel |
|
| 24 | Workload Distribution in Fault Simulation |
Amin, Minesh B. |
1997 |
10 | 3 |
p. 277-282 |
artikel |
24 gevonden resultaten