| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs
|
Aghaee, Nima
|
|
2015
|
31 |
5-6 |
p. 503-523
|
artikel
|
| 2 |
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests
|
Sindia, Suraj
|
|
2015
|
31 |
5-6 |
p. 479-489
|
artikel
|
| 3 |
Design and Implementation of an FPGA-Based Data/Timing Formatter
|
Chen, Yu-Yi
|
|
2015
|
31 |
5-6 |
p. 549-559
|
artikel
|
| 4 |
Double Node Upsets Hardened Latch Circuits
|
Li, Yuanqing
|
|
2015
|
31 |
5-6 |
p. 537-548
|
artikel
|
| 5 |
Editorial
|
Agrawal, Vishwani D.
|
|
2015
|
31 |
5-6 |
p. 421-422
|
artikel
|
| 6 |
Incipient Fault Diagnostics and Remaining Useful Life Prediction of Analog Filters
|
Hu, Zewen
|
|
2015
|
31 |
5-6 |
p. 461-477
|
artikel
|
| 7 |
2014 JETTA-TTTC Best Paper Award
|
|
|
2015
|
31 |
5-6 |
p. 425
|
artikel
|
| 8 |
Performance Degradation Tolerance Analysis and Design for Effective Yield Enhancement
|
Hsieh, Tong-Yu
|
|
2015
|
31 |
5-6 |
p. 427-441
|
artikel
|
| 9 |
Phase Noise Testing of Analog/IF Signals Using Digital ATE: A New Post-Processing Algorithm for Extended Measurement Range
|
David-Grignot, Stéphane
|
|
2015
|
31 |
5-6 |
p. 443-459
|
artikel
|
| 10 |
Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology
|
Li, Lixiang
|
|
2015
|
31 |
5-6 |
p. 561-568
|
artikel
|
| 11 |
Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection
|
Gören, Sezer
|
|
2015
|
31 |
5-6 |
p. 525-536
|
artikel
|
| 12 |
Spot Defect Diagnosis in Analog Nonlinear Circuits with Possible Multiple Operating Points
|
Tadeusiewicz, Michał
|
|
2015
|
31 |
5-6 |
p. 491-502
|
artikel
|
| 13 |
Test Technology Newsletter
|
|
|
2015
|
31 |
5-6 |
p. 423-424
|
artikel
|
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