| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper
|
Marinissen, Erik Jan
|
|
2011
|
28 |
1 |
p. 73-92
|
artikel
|
| 2 |
Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods
|
Lou, Yi
|
|
2011
|
28 |
1 |
p. 27-38
|
artikel
|
| 3 |
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems
|
Pasca, Vladimir
|
|
2011
|
28 |
1 |
p. 137-150
|
artikel
|
| 4 |
Editorial
|
Agrawal, Vishwani D.
|
|
2012
|
28 |
1 |
p. 1
|
artikel
|
| 5 |
Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits
|
Backes, Benjamin
|
|
2011
|
28 |
1 |
p. 53-62
|
artikel
|
| 6 |
Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects
|
Kannan, Sukeshwar
|
|
2011
|
28 |
1 |
p. 39-51
|
artikel
|
| 7 |
Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits
|
Marinissen, Erik Jan
|
|
2012
|
28 |
1 |
p. 13-14
|
artikel
|
| 8 |
2011 JETTA Reviewers
|
|
|
2012
|
28 |
1 |
p. 7-9
|
artikel
|
| 9 |
Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance
|
Sukharev, Valeriy
|
|
2011
|
28 |
1 |
p. 63-72
|
artikel
|
| 10 |
New Editors, 2012
|
|
|
2012
|
28 |
1 |
p. 3-5
|
artikel
|
| 11 |
On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs
|
Buttrick, Michael
|
|
2011
|
28 |
1 |
p. 93-101
|
artikel
|
| 12 |
Optimization Methods for Post-Bond Testing of 3D Stacked ICs
|
Noia, Brandon
|
|
2011
|
28 |
1 |
p. 103-120
|
artikel
|
| 13 |
Scheduling Tests for 3D Stacked Chips under Power Constraints
|
SenGupta, Breeta
|
|
2011
|
28 |
1 |
p. 121-135
|
artikel
|
| 14 |
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost
|
Taouil, Mottaqiallah
|
|
2011
|
28 |
1 |
p. 15-25
|
artikel
|
| 15 |
Test Technology Newsletter
|
|
|
2012
|
28 |
1 |
p. 11-12
|
artikel
|
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