| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy
|
Chang, Da-Ming
|
|
2007
|
24 |
1-3 |
p. 181-192
|
artikel
|
| 2 |
Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and X–Y Zoning Method
|
Miura, Yukiya
|
|
2007
|
24 |
1-3 |
p. 223-233
|
artikel
|
| 3 |
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs
|
Jas, Abhijit
|
|
2007
|
24 |
1-3 |
p. 259-269
|
artikel
|
| 4 |
Analysis and Evaluations of Reliability of Reconfigurable FPGAs
|
Pontarelli, Salvatore
|
|
2007
|
24 |
1-3 |
p. 105-116
|
artikel
|
| 5 |
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique
|
Gong, Rui
|
|
2007
|
24 |
1-3 |
p. 57-65
|
artikel
|
| 6 |
Bilateral Testing of Nano-scale Fault-Tolerant Circuits
|
Fang, Lei
|
|
2007
|
24 |
1-3 |
p. 285-296
|
artikel
|
| 7 |
Checkers’ No-Harm Alarms and Design Approaches to Tolerate Them
|
Rossi, Daniele
|
|
2007
|
24 |
1-3 |
p. 93-103
|
artikel
|
| 8 |
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger
|
Sasaki, Yoichi
|
|
2007
|
24 |
1-3 |
p. 11-19
|
artikel
|
| 9 |
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs
|
Liu, Lushan
|
|
2007
|
24 |
1-3 |
p. 165-179
|
artikel
|
| 10 |
Design Considerations for High Performance RF Cores Based on Process Variation Study
|
Upadhyaya, Shambhu
|
|
2007
|
24 |
1-3 |
p. 143-155
|
artikel
|
| 11 |
Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding
|
Ganguly, Amlan
|
|
2007
|
24 |
1-3 |
p. 67-81
|
artikel
|
| 12 |
Editorial
|
Agrawal, Vishwani D.
|
|
2008
|
24 |
1-3 |
p. 1
|
artikel
|
| 13 |
Error Detection Enhancement in PowerPC Architecture-based Embedded Processors
|
Fazeli, Mahdi
|
|
2007
|
24 |
1-3 |
p. 21-33
|
artikel
|
| 14 |
Guest Editorial
|
Touba, Nur
|
|
2008
|
24 |
1-3 |
p. 9-10
|
artikel
|
| 15 |
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
|
Rhod, Eduardo Luis
|
|
2007
|
24 |
1-3 |
p. 45-56
|
artikel
|
| 16 |
Hierarchical Verification for Increasing Performance in Reliable Processors
|
Yoo, Joonhyuk
|
|
2007
|
24 |
1-3 |
p. 117-128
|
artikel
|
| 17 |
Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy
|
Granhaug, Kristian
|
|
2007
|
24 |
1-3 |
p. 157-163
|
artikel
|
| 18 |
List of 2007 Reviewers
|
|
|
2008
|
24 |
1-3 |
p. 7-8
|
artikel
|
| 19 |
Majority Logic Mapping for Soft Error Dependability
|
Petroli, Lorenzo
|
|
2007
|
24 |
1-3 |
p. 83-92
|
artikel
|
| 20 |
Monomer Control for Error Tolerance in DNA Self-Assembly
|
Jang, Byunghyun
|
|
2007
|
24 |
1-3 |
p. 271-284
|
artikel
|
| 21 |
New Editors
|
|
|
2008
|
24 |
1-3 |
p. 3-4
|
artikel
|
| 22 |
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
|
Christou, Kyriakos
|
|
2007
|
24 |
1-3 |
p. 203-222
|
artikel
|
| 23 |
Performance-Optimized Design for Parametric Reliability
|
Datta, Ramyanshu
|
|
2007
|
24 |
1-3 |
p. 129-141
|
artikel
|
| 24 |
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA
|
Ma, X.
|
|
2007
|
24 |
1-3 |
p. 297-311
|
artikel
|
| 25 |
Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder Design
|
Choi, Myungsu
|
|
2007
|
24 |
1-3 |
p. 313-320
|
artikel
|
| 26 |
Scan Test Response Compaction Combined with Diagnosis Capabilities
|
Wichlund, Sverre
|
|
2007
|
24 |
1-3 |
p. 235-246
|
artikel
|
| 27 |
Software and Hardware Techniques for SEU Detection in IP Processors
|
Bolchini, C.
|
|
2007
|
24 |
1-3 |
p. 35-44
|
artikel
|
| 28 |
Substrate Testing on a Multi-Site/Multi-Probe ATE
|
Ma, Xiaojun
|
|
2007
|
24 |
1-3 |
p. 193-201
|
artikel
|
| 29 |
Test Technology Newsletter February 2008
|
|
|
2008
|
24 |
1-3 |
p. 5-6
|
artikel
|
| 30 |
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
|
He, Zhiyuan
|
|
2007
|
24 |
1-3 |
p. 247-257
|
artikel
|
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