| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips
|
Sandeep Kumar Goel
|
|
2003
|
19 |
4 |
p. 425-435
11 p.
|
artikel
|
| 2 |
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips
|
Goel, Sandeep Kumar
|
|
2003
|
19 |
4 |
p. 425-435
|
artikel
|
| 3 |
Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips
|
Sandeep Kumar Goel
|
|
2003
|
19 |
4 |
p. 407-416
10 p.
|
artikel
|
| 4 |
Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips
|
Goel, Sandeep Kumar
|
|
2003
|
19 |
4 |
p. 407-416
|
artikel
|
| 5 |
Editorial
|
Vishwani D. Agrawal
|
|
2003
|
19 |
4 |
p. 363-363
1 p.
|
artikel
|
| 6 |
Editorial
|
Agrawal, Vishwani D.
|
|
2003
|
19 |
4 |
p. 363
|
artikel
|
| 7 |
Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors
|
Xiao Liu
|
|
2003
|
19 |
4 |
p. 437-445
9 p.
|
artikel
|
| 8 |
Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors
|
Liu, Xiao
|
|
2003
|
19 |
4 |
p. 437-445
|
artikel
|
| 9 |
Guest Editorial
|
Christian Landrault
|
|
2003
|
19 |
4 |
p. 367-367
1 p.
|
artikel
|
| 10 |
Guest Editorial
|
Landrault, Christian
|
|
2003
|
19 |
4 |
p. 367
|
artikel
|
| 11 |
Investigations for Minimum Invasion Digital Only Built-In Ramp Based Test Techniques for Charge Pump PLL's
|
Martin John Burbidge
|
|
2003
|
19 |
4 |
p. 481-490
10 p.
|
artikel
|
| 12 |
Investigations for Minimum Invasion Digital Only Built-In “Ramp” Based Test Techniques for Charge Pump PLL's
|
Burbidge, Martin John
|
|
2003
|
19 |
4 |
p. 481-490
|
artikel
|
| 13 |
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short
|
M. Renovell
|
|
2003
|
19 |
4 |
p. 377-386
10 p.
|
artikel
|
| 14 |
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short
|
Renovell, M.
|
|
2003
|
19 |
4 |
p. 377-386
|
artikel
|
| 15 |
Multi-TAP Controller Architecture for Digital System Chips
|
Bart Vermeulen
|
|
2003
|
19 |
4 |
p. 417-424
8 p.
|
artikel
|
| 16 |
Multi-TAP Controller Architecture for Digital System Chips
|
Vermeulen, Bart
|
|
2003
|
19 |
4 |
p. 417-424
|
artikel
|
| 17 |
On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up
|
Camelia Hora
|
|
2003
|
19 |
4 |
p. 369-376
8 p.
|
artikel
|
| 18 |
On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up
|
Hora, Camelia
|
|
2003
|
19 |
4 |
p. 369-376
|
artikel
|
| 19 |
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST
|
S. Bernard
|
|
2003
|
19 |
4 |
p. 469-479
11 p.
|
artikel
|
| 20 |
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST
|
Bernard, S.
|
|
2003
|
19 |
4 |
p. 469-479
|
artikel
|
| 21 |
On Selecting Testable Paths in Scan Designs
|
Yun Shao
|
|
2003
|
19 |
4 |
p. 447-456
10 p.
|
artikel
|
| 22 |
On Selecting Testable Paths in Scan Designs
|
Shao, Yun
|
|
2003
|
19 |
4 |
p. 447-456
|
artikel
|
| 23 |
Reducing Average and Peak Test Power Through Scan Chain Modification
|
Ozgur Sinanoglu
|
|
2003
|
19 |
4 |
p. 457-467
11 p.
|
artikel
|
| 24 |
Reducing Average and Peak Test Power Through Scan Chain Modification
|
Sinanoglu, Ozgur
|
|
2003
|
19 |
4 |
p. 457-467
|
artikel
|
| 25 |
Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
|
Jonathan Bradford
|
|
2003
|
19 |
4 |
p. 387-395
9 p.
|
artikel
|
| 26 |
Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
|
Bradford, Jonathan
|
|
2003
|
19 |
4 |
p. 387-395
|
artikel
|
| 27 |
Synchronous Full-Scan for Asynchronous Handshake Circuits
|
Frank te Beest
|
|
2003
|
19 |
4 |
p. 397-406
10 p.
|
artikel
|
| 28 |
Synchronous Full-Scan for Asynchronous Handshake Circuits
|
te Beest, Frank
|
|
2003
|
19 |
4 |
p. 397-406
|
artikel
|
| 29 |
Test Technology Technical Council Newsletter
|
A. Ivanov
|
|
2003
|
19 |
4 |
p. 365-366
2 p.
|
artikel
|
| 30 |
Test Technology Technical Council Newsletter
|
Ivanov, A.
|
|
2003
|
19 |
4 |
p. 365-366
|
artikel
|
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