| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures
|
V.A. Zivkovic
|
|
2002
|
18 |
2 |
p. 203-212
10 p.
|
artikel
|
| 2 |
An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures
|
Zivkovic, V.A.
|
|
2002
|
18 |
2 |
p. 203-212
|
artikel
|
| 3 |
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits
|
Yukiya Miura
|
|
2002
|
18 |
2 |
p. 109-120
12 p.
|
artikel
|
| 4 |
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits
|
Miura, Yukiya
|
|
2002
|
18 |
2 |
p. 109-120
|
artikel
|
| 5 |
Diagnosis Strategies for Hardware or Software Systems
|
Maisaa Khalil
|
|
2002
|
18 |
2 |
p. 241-251
11 p.
|
artikel
|
| 6 |
Diagnosis Strategies for Hardware or Software Systems
|
Khalil, Maisaa
|
|
2002
|
18 |
2 |
p. 241-251
|
artikel
|
| 7 |
Digital Window Comparator DfT Scheme for Mixed-Signal ICs
|
Daniela De Venuto
|
|
2002
|
18 |
2 |
p. 121-128
8 p.
|
artikel
|
| 8 |
Digital Window Comparator DfT Scheme for Mixed-Signal ICs
|
De Venuto, Daniela
|
|
2002
|
18 |
2 |
p. 121-128
|
artikel
|
| 9 |
Editorial
|
Vishwani D. Agrawal
|
|
2002
|
18 |
2 |
p. 103-104
2 p.
|
artikel
|
| 10 |
Editorial
|
Agrawal, Vishwani D.
|
|
2002
|
18 |
2 |
p. 103-104
|
artikel
|
| 11 |
Enhanced Reduced Pin-Count Test for Full-Scan Design
|
Harald Vranken
|
|
2002
|
18 |
2 |
p. 129-143
15 p.
|
artikel
|
| 12 |
Enhanced Reduced Pin-Count Test for Full-Scan Design
|
Vranken, Harald
|
|
2002
|
18 |
2 |
p. 129-143
|
artikel
|
| 13 |
Guest Editorial
|
Christian Landrault
|
|
2002
|
18 |
2 |
p. 107-107
1 p.
|
artikel
|
| 14 |
Guest Editorial
|
Landrault, Christian
|
|
2002
|
18 |
2 |
p. 107
|
artikel
|
| 15 |
Hardware Generation of Random Single Input Change Test Sequences
|
R. David
|
|
2002
|
18 |
2 |
p. 145-157
13 p.
|
artikel
|
| 16 |
Hardware Generation of Random Single Input Change Test Sequences
|
David, R.
|
|
2002
|
18 |
2 |
p. 145-157
|
artikel
|
| 17 |
Reusing Scan Chains for Test Pattern Decompression
|
Rainer Dorsch
|
|
2002
|
18 |
2 |
p. 231-240
10 p.
|
artikel
|
| 18 |
Reusing Scan Chains for Test Pattern Decompression
|
Dorsch, Rainer
|
|
2002
|
18 |
2 |
p. 231-240
|
artikel
|
| 19 |
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
|
M.B. Santos
|
|
2002
|
18 |
2 |
p. 179-187
9 p.
|
artikel
|
| 20 |
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
|
Santos, M.B.
|
|
2002
|
18 |
2 |
p. 179-187
|
artikel
|
| 21 |
Synthesis of Scan Chains for Netlist Descriptions at RT-Level
|
Yu Huang
|
|
2002
|
18 |
2 |
p. 189-201
13 p.
|
artikel
|
| 22 |
Synthesis of Scan Chains for Netlist Descriptions at RT-Level
|
Huang, Yu
|
|
2002
|
18 |
2 |
p. 189-201
|
artikel
|
| 23 |
Test Technology Technical Council Newsletter
|
André Ivanov
|
|
2002
|
18 |
2 |
p. 105-106
2 p.
|
artikel
|
| 24 |
Test Technology Technical Council Newsletter
|
Ivanov, André
|
|
2002
|
18 |
2 |
p. 105-106
|
artikel
|
| 25 |
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
|
Vikram Iyengar
|
|
2002
|
18 |
2 |
p. 213-230
18 p.
|
artikel
|
| 26 |
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
|
Iyengar, Vikram
|
|
2002
|
18 |
2 |
p. 213-230
|
artikel
|
| 27 |
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
|
Hua-Guo Liang
|
|
2002
|
18 |
2 |
p. 159-170
12 p.
|
artikel
|
| 28 |
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
|
Liang, Hua-Guo
|
|
2002
|
18 |
2 |
p. 159-170
|
artikel
|
| 29 |
Using At-Speed BIST to Test LVDS Serializer/Deserializer Function
|
Magnus Eckersand
|
|
2002
|
18 |
2 |
p. 171-177
7 p.
|
artikel
|
| 30 |
Using At-Speed BIST to Test LVDS Serializer/Deserializer Function
|
Eckersand, Magnus
|
|
2002
|
18 |
2 |
p. 171-177
|
artikel
|
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