| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
Allocation Techniques for Reducing BIST Area Overhead ofData Paths
|
Ishwar Parulkar
|
|
1998
|
13 |
2 |
p. 149-166
18 p.
|
artikel
|
| 2 |
Allocation Techniques for Reducing BIST Area Overhead of Data Paths
|
Parulkar, Ishwar
|
|
1998
|
13 |
2 |
p. 149-166
|
artikel
|
| 3 |
Controller Resynthesis for Testability Enhancement of RTLController/Data Path Circuits
|
Srivaths Ravi
|
|
1998
|
13 |
2 |
p. 201-212
12 p.
|
artikel
|
| 4 |
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits
|
Ravi, Srivaths
|
|
1998
|
13 |
2 |
p. 201-212
|
artikel
|
| 5 |
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
|
Sujit Dey
|
|
1998
|
13 |
2 |
p. 79-91
13 p.
|
artikel
|
| 6 |
Design for Testability Techniques at the Behavioral and Register-Transfer Levels
|
Dey, Sujit
|
|
1998
|
13 |
2 |
p. 79-91
|
artikel
|
| 7 |
Editorial
|
Vishwani D. Agrawal
|
|
1998
|
13 |
2 |
p. 75-75
1 p.
|
artikel
|
| 8 |
Editorial
|
Agrawal, Vishwani D.
|
|
1998
|
13 |
2 |
p. 75
|
artikel
|
| 9 |
Guest Editorial
|
Niraj K. Jha
|
|
1998
|
13 |
2 |
p. 77-77
1 p.
|
artikel
|
| 10 |
Guest Editorial
|
Jha, Niraj K.
|
|
1998
|
13 |
2 |
p. 77
|
artikel
|
| 11 |
High-Level Controllability and Observability Analysis for Test Synthesis
|
Frank F. Hsu
|
|
1998
|
13 |
2 |
p. 93-103
11 p.
|
artikel
|
| 12 |
High-Level Controllability and Observability Analysis for Test Synthesis
|
Hsu, Frank F.
|
|
1998
|
13 |
2 |
p. 93-103
|
artikel
|
| 13 |
High-Level Test Synthesis for Behavioral and Structural Designs
|
Christos A. Papachristou
|
|
1998
|
13 |
2 |
p. 167-188
22 p.
|
artikel
|
| 14 |
High-Level Test Synthesis for Behavioral and Structural Designs
|
Papachristou, Christos A.
|
|
1998
|
13 |
2 |
p. 167-188
|
artikel
|
| 15 |
RTL Test Justification and Propagation Analysis for Modular Designs
|
Yiorgos Makris
|
|
1998
|
13 |
2 |
p. 105-120
16 p.
|
artikel
|
| 16 |
RTL Test Justification and Propagation Analysis for Modular Designs
|
Makris, Yiorgos
|
|
1998
|
13 |
2 |
p. 105-120
|
artikel
|
| 17 |
Synthesis of Native Mode Self-Test Programs
|
Jian Shen
|
|
1998
|
13 |
2 |
p. 137-148
12 p.
|
artikel
|
| 18 |
Synthesis of Native Mode Self-Test Programs
|
Shen, Jian
|
|
1998
|
13 |
2 |
p. 137-148
|
artikel
|
| 19 |
Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays
|
Li-C. Wang
|
|
1998
|
13 |
2 |
p. 121-135
15 p.
|
artikel
|
| 20 |
Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays
|
Wang, Li-C.
|
|
1998
|
13 |
2 |
p. 121-135
|
artikel
|
| 21 |
Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures
|
Nilanjan Mukherjee
|
|
1998
|
13 |
2 |
p. 189-200
12 p.
|
artikel
|
| 22 |
Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures
|
Mukherjee, Nilanjan
|
|
1998
|
13 |
2 |
p. 189-200
|
artikel
|
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