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                             87 gevonden resultaten
nr titel auteur tijdschrift jaar jaarg. afl. pagina('s) type
1 About long-term effects of hot-carrier stress on n-MOSFETS Stadlober, Barbara
 2000
 40 8-10 p. 1485-1490
6 p.
 artikel
2 Acceleration method for gate-disturb degradation on embedded flash EEPROM Wada, Tetsuaki
 2000
 40 8-10 p. 1279-1283
5 p.
 artikel
3 A complementary molecular-model (including field and current) for TDDB in SiO2 dielectrics McPherson, J.W.
 2000
 40 8-10 p. 1591-1597
7 p.
 artikel
4 A method for HBT process control and defect detection using pulsed electrical stress Sydlo, C.
 2000
 40 8-10 p. 1449-1453
5 p.
 artikel
5 A method to minimize test time for accelerated ageing of pHEMT's by analysis of the electronic fingerprint of the initial stage of degradation Petersen, R.
 2000
 40 8-10 p. 1721-1726
6 p.
 artikel
6 A modelling approach to assess the creep behaviour of large-area solder joints Poech, M.H.
 2000
 40 8-10 p. 1653-1658
6 p.
 artikel
7 Analysis of high-power devices using proton beam induced currents Zmeck, M.
 2000
 40 8-10 p. 1413-1418
6 p.
 artikel
8 Annealing behavior of gate oxide leakage current after quasi-breakdown Xu, Zhen
 2000
 40 8-10 p. 1341-1346
6 p.
 artikel
9 Application of analytical TEM for failure analysis of semiconductor device structures Engelmann, H.J.
 2000
 40 8-10 p. 1747-1751
5 p.
 artikel
10 A review of sample backside preparation techniques for VLSI Perdu, P.
 2000
 40 8-10 p. 1431-1436
6 p.
 artikel
11 A simple model for the mode I popcorn effect for IC packages Alpern, P.
 2000
 40 8-10 p. 1503-1508
6 p.
 artikel
12 Assessment of copper contamination impact on inter-level dielectric reliability performed with time-dependent-dielectric-breakdown tests Gonella, R.
 2000
 40 8-10 p. 1305-1309
5 p.
 artikel
13 Author index 2000
 40 8-10 p. I-III
nvt p.
 artikel
14 Automatic EB fault-tracing system using fuzzy-logic approach Miura, K.
 2000
 40 8-10 p. 1377-1382
6 p.
 artikel
15 Back side optical beam induced current method for the localization of electric field enhancements in edge termination structures of power semiconductor devices Soelkner, Gerald
 2000
 40 8-10 p. 1641-1645
5 p.
 artikel
16 Bulk and surface degradation mode in 0.35μm technology gg-nMOS ESD protection devices Pogany, D
 2000
 40 8-10 p. 1467-1472
6 p.
 artikel
17 Calculation of the optimal FIB milling and deposition operations for easier and faster circuit reconfiguration Desplats, Romain
 2000
 40 8-10 p. 1759-1764
6 p.
 artikel
18 CALYPSO — Critical Area, Lifetime, and Yield Predicting Software Miskowiec, P.
 2000
 40 8-10 p. 1629-1634
6 p.
 artikel
19 Comparison of RF and DC life-test effects on GaAs power MESFETs Lambert, B.
 2000
 40 8-10 p. 1727-1731
5 p.
 artikel
20 Correlation of scanning thermal microscopy and near-field cathodoluminescence analyses on a blue GaN light emitting device Heiderhoff, R.
 2000
 40 8-10 p. 1383-1388
6 p.
 artikel
21 Cross-talk in electric force microscopy testing of parallel sub-micrometer conducting lines Behnke, U.
 2000
 40 8-10 p. 1401-1406
6 p.
 artikel
22 3-D analysis of the breakdown localised defects of ACSTM through a triac study Forster, S.
 2000
 40 8-10 p. 1695-1700
6 p.
 artikel
23 Data retention prediction for modern floating gate non-volatile memories Tao, G
 2000
 40 8-10 p. 1561-1566
6 p.
 artikel
24 Design for reliability Minehane, S.
 2000
 40 8-10 p. 1285-1294
10 p.
 artikel
25 Dimensional effects on the reliability of polycrystalline silicon thin-film transistors Zan, H.W.
 2000
 40 8-10 p. 1479-1483
5 p.
 artikel
26 Does short wavelength lithography process degrade the integrity of thin gate oxide? Kim, S.J.
 2000
 40 8-10 p. 1609-1613
5 p.
 artikel
27 Editorial Balk, L.J.
 2000
 40 8-10 p. ix-
1 p.
 artikel
28 Effects of test sequences on the degradation analysis in high speed connectors Catelani, M.
 2000
 40 8-10 p. 1461-1465
5 p.
 artikel
29 Electrochemical wet etching in KOH:H20 solution and secondary/ion image passive voltage contrast as a complementary technique in failure analysis Oh Chong Khiam,
 2000
 40 8-10 p. 1455-1459
5 p.
 artikel
30 Electromigration characterization of damascene copper interconnects using normally and highly accelerated tests Berger, T.
 2000
 40 8-10 p. 1311-1316
6 p.
 artikel
31 Establishment of derating rules and end of life drifts figures for electronic components Cosqueric, L.
 2000
 40 8-10 p. 1273-1278
6 p.
 artikel
32 Evaluation of the hot carrier/ionizing radiation induced effects on the RF characteristics of low-complexity SiGe heterojunction bipolar transistors by numerical simulation Kuchenbecker, J
 2000
 40 8-10 p. 1579-1584
6 p.
 artikel
33 Evaluation of the thermal resistance of AlCu electromigration test structures Braghieri, A.
 2000
 40 8-10 p. 1317-1322
6 p.
 artikel
34 Failure criteria for long term Accelerated Power Cycling Test linked to electrical turn off SOA on IGBT module. A 4000 hours test on 1200A–3300V module with AlSiC base plate Coquery, G.
 2000
 40 8-10 p. 1665-1670
6 p.
 artikel
35 Faster fault isolation using a dichotomy reduction of node candidates Desplats, Romain
 2000
 40 8-10 p. 1419-1424
6 p.
 artikel
36 Flip chips and acoustic micro imaging: An overview of past applications, present status, and roadmap for the future Semmens, Janet E.
 2000
 40 8-10 p. 1539-1543
5 p.
 artikel
37 Impact of ESD-induced soft drain junction damage on CMOS product lifetime Reiner, Joachim C.
 2000
 40 8-10 p. 1619-1628
10 p.
 artikel
38 Impact of process steps on electrical and electromigration performances of copper interconnects in damascene architecture Gonella, R.
 2000
 40 8-10 p. 1329-1334
6 p.
 artikel
39 Influence of fluorine contamination on reliability of thin gate oxides Krüger, D.
 2000
 40 8-10 p. 1335-1340
6 p.
 artikel
40 In-situ sem observation of electromigration in thin metal films at accelerated stress conditions d'Haen, J.
 2000
 40 8-10 p. 1407-1412
6 p.
 artikel
41 Laser cross section measurement for the evaluation of single-event effects in integrated circuits Pouget, V.
 2000
 40 8-10 p. 1371-1375
5 p.
 artikel
42 Low-field latent plasma damage depassivation in thin-oxide MOS Cellere, G.
 2000
 40 8-10 p. 1347-1352
6 p.
 artikel
43 Low frequency noise evolution during lifetime tests of lines and vias subjected to electromigration Dattilo, V.
 2000
 40 8-10 p. 1323-1327
5 p.
 artikel
44 Measurement of the thermomechanical strain of electronic devices by shearography Dilhaire, S.
 2000
 40 8-10 p. 1509-1514
6 p.
 artikel
45 Model and design rules for eliminating surface potential induced failures in high voltage integrated circuits van der Pol, Jacob A.
 2000
 40 8-10 p. 1267-1272
6 p.
 artikel
46 Model for the decrease in HBT collector current under DC stress based on recombination enhanced defect reactions Schüβler, M.
 2000
 40 8-10 p. 1733-1738
6 p.
 artikel
47 Modeling the conduction characteristics of broken down gate oxides in MOS structures Mirand, E.
 2000
 40 8-10 p. 1599-1603
5 p.
 artikel
48 MOS transistor reliability under analog operation Thewes, R.
 2000
 40 8-10 p. 1545-1554
10 p.
 artikel
49 New FIB/TEM evidence for a REDR mechanism in sudden failures of 980 nm SL SQW InGaAs/AlGaAs pump laser diodes Vanzi, M.
 2000
 40 8-10 p. 1753-1757
5 p.
 artikel
50 New non-destructive laser ablation based backside sample preparation method Beaudoin, F
 2000
 40 8-10 p. 1425-1429
5 p.
 artikel
51 Numerical investigation for a Grounded Gate NMOS Transistor under electrostatic discharge (ESD) through TLP method Galy, P.
 2000
 40 8-10 p. 1473-1477
5 p.
 artikel
52 Overstress and electrostatic discharge in CMOS and BCD integrated circuits Meneghesso, G.
 2000
 40 8-10 p. 1739-1746
8 p.
 artikel
53 Packaging of CMOS MEMS Baltes, Henry
 2000
 40 8-10 p. 1255-1262
8 p.
 artikel
54 Parasitic effects and long term stability of InP-based HEMTs Meneghesso, G.
 2000
 40 8-10 p. 1715-1720
6 p.
 artikel
55 PICA: Backside failure analysis of CMOS circuits using Picosecond Imaging Circuit Analysis Mc Manus, M.K.
 2000
 40 8-10 p. 1353-1358
6 p.
 artikel
56 Principle and application of a bifunctional laser linking and cutting structure for microelectronic circuits in standard CMOS-technology Mende, Ole
 2000
 40 8-10 p. 1437-1442
6 p.
 artikel
57 Quantification of scanning capacitance microscopy measurements for 2D dopant profiling Malberti, P.
 2000
 40 8-10 p. 1395-1399
5 p.
 artikel
58 Relation between robustness against ESD and against flash events in deflection amplifiers van Roijen, R.
 2000
 40 8-10 p. 1263-1266
4 p.
 artikel
59 Relationship between microstructure and electromigration damage in unpassivated PVD copper damascene interconnects Koetter, T.G.
 2000
 40 8-10 p. 1295-1299
5 p.
 artikel
60 Reliability and stability of GaAs-based pseudomorphic quantum wells for high-precision power metering Haddab, Y.
 2000
 40 8-10 p. 1443-1447
5 p.
 artikel
61 Reliability aspects of high temperature power MOSFETs Manca, J.V.
 2000
 40 8-10 p. 1679-1682
4 p.
 artikel
62 Reliability model for Al wire bonds subjected to heel crack failures Ramminger, S.
 2000
 40 8-10 p. 1521-1525
5 p.
 artikel
63 Reliability of AIGaN/GaN HFETs comprising refractory ohmic and Schottky contacts Würfl, J.
 2000
 40 8-10 p. 1689-1693
5 p.
 artikel
64 Reliability of flip chip and chip size packages Reichl, H.
 2000
 40 8-10 p. 1243-1254
12 p.
 artikel
65 Reliability of InAlAs/InGaAs HEMTs grown on GaAs substrate with metamorphic buffer Dammann, M.
 2000
 40 8-10 p. 1709-1713
5 p.
 artikel
66 Reliability of optoelectronic components for telecommunications Sauvage, D.
 2000
 40 8-10 p. 1701-1708
8 p.
 artikel
67 Reliability of passivated p-type polycrystalline silicon thin film transistors Peng, D.Z.
 2000
 40 8-10 p. 1491-1495
5 p.
 artikel
68 Reliability testing of high-power multi-chip IGBT modules Lefranc, G.
 2000
 40 8-10 p. 1659-1663
5 p.
 artikel
69 Reliable use of commercial technology in high temperature environments McCluskey, Patrick
 2000
 40 8-10 p. 1671-1678
8 p.
 artikel
70 Room temperature grain growth in electroplated copper thin films Wendrock, H.
 2000
 40 8-10 p. 1301-1304
4 p.
 artikel
71 RTS noise in submicron SiGe epitaxial base bipolar transistors Militaru, L.
 2000
 40 8-10 p. 1585-1590
6 p.
 artikel
72 Shot noise partial suppression in the SILO regime Crupi, F.
 2000
 40 8-10 p. 1605-1608
4 p.
 artikel
73 Stability of polysilicon thin film transistors under switch operating Toutah, H.
 2000
 40 8-10 p. 1573-1577
5 p.
 artikel
74 Study of triggering inhomogeneities in gg-nMOS ESD protection devices via thermal mapping using backside laser interferometry Litzenberger, M.
 2000
 40 8-10 p. 1359-1364
6 p.
 artikel
75 Surface oxide films on Aluminum bondpads: Influence on thermosonic wire bonding behavior and hardness Petzold, M.
 2000
 40 8-10 p. 1515-1520
6 p.
 artikel
76 Technique for determining a prudent voltage stress to improve product quality and reliability Blish II, Richard C.
 2000
 40 8-10 p. 1615-1618
4 p.
 artikel
77 The impacts of SILC and hot carrier induced drain leakage current on the refresh time in DRAM Hong, Sung H.
 2000
 40 8-10 p. 1555-1560
6 p.
 artikel
78 Thermal and free carrier concentration mapping during ESD event in smart Power ESD protection devices using an improved laser interferometric technique Fürböck, C.
 2000
 40 8-10 p. 1365-1370
6 p.
 artikel
79 Thermal fatigue and metallurgical reactions in solder joints of LTCC modules Rautioaho, R.
 2000
 40 8-10 p. 1527-1532
6 p.
 artikel
80 Thermal stability of laser welded thermocouple contacts to Si for high temperature thermal sensor application Ernst, H.
 2000
 40 8-10 p. 1683-1688
6 p.
 artikel
81 The role of spreading resistance profiling in manufacturing control and technology development Lin-Kwang, J.
 2000
 40 8-10 p. 1497-1502
6 p.
 artikel
82 Transconductance increase due to charge trapping during hot-carrier stress of nMOSFETs Rafí, J.M.
 2000
 40 8-10 p. 1567-1572
6 p.
 artikel
83 Use of electrical stress and isochronal annealing on power MOSFETs in order to characterize the effects of 60Co irradiation Picard, C.
 2000
 40 8-10 p. 1647-1652
6 p.
 artikel
84 Vertical die crack stresses of Flip Chip induced in major package assembly processes Yang, D.G.
 2000
 40 8-10 p. 1533-1538
6 p.
 artikel
85 Voltage-influence of biased interconnection line on integrated circuit-internal current contrast measurements via magnetic force microscopy Weber, R.
 2000
 40 8-10 p. 1389-1394
6 p.
 artikel
86 X-ray structure characterization of barriers for Cu metallization Mattern, N.
 2000
 40 8-10 p. 1765-1770
6 p.
 artikel
87 Yield and reliability analysis of digital standard cells with resistive defects Huber, M.
 2000
 40 8-10 p. 1635-1640
6 p.
 artikel
                             87 gevonden resultaten
 
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