| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
Analysis of defect capture cross sections using non-radiative multiphonon-assisted trapping model
|
Garetto, Davide
|
|
2012
|
71 |
C |
p. 74-79
6 p.
|
artikel
|
| 2 |
Behavior of triple-gate Bulk FinFETs with and without DTMOS operation
|
de Andrade, Maria Glória Caño
|
|
2012
|
71 |
C |
p. 63-68
6 p.
|
artikel
|
| 3 |
Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
|
Redolfi, A.
|
|
2012
|
71 |
C |
p. 106-112
7 p.
|
artikel
|
| 4 |
Characterization and modeling of capacitances in FD-SOI devices
|
Ben Akkez, Imed
|
|
2012
|
71 |
C |
p. 53-57
5 p.
|
artikel
|
| 5 |
Editorial Board
|
|
|
2012
|
71 |
C |
p. IFC-
1 p.
|
artikel
|
| 6 |
Effect of the choice of the tunnelling path on semi-classical numerical simulations of TFET devices
|
De Michielis, Luca
|
|
2012
|
71 |
C |
p. 7-12
6 p.
|
artikel
|
| 7 |
Foreword
|
Ferain, Isabelle
|
|
2012
|
71 |
C |
p. 1-
1 p.
|
artikel
|
| 8 |
Impact of self-heating and substrate effects on small-signal output conductance in UTBB SOI MOSFETs
|
Makovejev, S.
|
|
2012
|
71 |
C |
p. 93-100
8 p.
|
artikel
|
| 9 |
Impact of strain and Ge concentration on the performance of planar SiGe band-to-band-tunneling transistors
|
Schmidt, M.
|
|
2012
|
71 |
C |
p. 42-47
6 p.
|
artikel
|
| 10 |
LaLuO3 higher-κ dielectric integration in SOI MOSFETs with a gate-first process
|
Nichau, A.
|
|
2012
|
71 |
C |
p. 19-24
6 p.
|
artikel
|
| 11 |
Modeling the breakdown statistics of Al2O3/HfO2 nanolaminates grown by atomic-layer-deposition
|
Conde, A.
|
|
2012
|
71 |
C |
p. 48-52
5 p.
|
artikel
|
| 12 |
Monolithic 3D-ICs with single grain Si thin film transistors
|
Ishihara, R.
|
|
2012
|
71 |
C |
p. 80-87
8 p.
|
artikel
|
| 13 |
NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants
|
Martinez, A.
|
|
2012
|
71 |
C |
p. 101-105
5 p.
|
artikel
|
| 14 |
20nm Gate length Schottky MOSFETs with ultra-thin NiSi/epitaxial NiSi2 source/drain
|
Knoll, L.
|
|
2012
|
71 |
C |
p. 88-92
5 p.
|
artikel
|
| 15 |
Numerical investigation on the junctionless nanowire FET
|
Gnani, E.
|
|
2012
|
71 |
C |
p. 13-18
6 p.
|
artikel
|
| 16 |
Quantum simulations of electrostatics in Si cylindrical junctionless nanowire nFETs and pFETs with a homogeneous channel including strain and arbitrary crystallographic orientations
|
Pham, Anh-Tuan
|
|
2012
|
71 |
C |
p. 30-36
7 p.
|
artikel
|
| 17 |
Revisited approach for the characterization of Gate Induced Drain Leakage
|
Rafhay, Quentin
|
|
2012
|
71 |
C |
p. 37-41
5 p.
|
artikel
|
| 18 |
Study of annealing temperature influence on the performance of top gated graphene/SiC transistors
|
Clavel, M.
|
|
2012
|
71 |
C |
p. 2-6
5 p.
|
artikel
|
| 19 |
Subthreshold behavior of junctionless silicon nanowire transistors from atomic scale simulations
|
Ansari, Lida
|
|
2012
|
71 |
C |
p. 58-62
5 p.
|
artikel
|
| 20 |
Temperature dependence of the transport properties of spin field-effect transistors built with InAs and Si channels
|
Osintsev, D.
|
|
2012
|
71 |
C |
p. 25-29
5 p.
|
artikel
|
| 21 |
Two-dimensional carrier mapping at the nanometer-scale on 32nm node targeted p-MOSFETs using high vacuum scanning spreading resistance microscopy
|
Eyben, Pierre
|
|
2012
|
71 |
C |
p. 69-73
5 p.
|
artikel
|
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