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                             31 gevonden resultaten
nr titel auteur tijdschrift jaar jaarg. afl. pagina('s) type
1 Aluminum-induced iso-epitaxy of silicon for low-temperature fabrication of centimeter-large p+n junctions Sakic, Agata
2013
84 C p. 65-73
9 p.
artikel
2 A manufacturable process integration approach for graphene devices Vaziri, Sam
2013
84 C p. 185-190
6 p.
artikel
3 Cell libraries for robust low-voltage operation in nanometer technologies Gemmeke, Tobias
2013
84 C p. 132-141
10 p.
artikel
4 Comparative study of electrical characteristics in (100) and (110) surface-oriented nMOSFETs with direct contact La-silicate/Si interface structure Kawanago, T.
2013
84 C p. 53-57
5 p.
artikel
5 Designing digital circuits with nano-scale devices: Challenges and opportunities Belleville, Marc
2013
84 C p. 38-45
8 p.
artikel
6 Deterministic solvers for the Boltzmann transport equation of 3D and quasi-2D electron and hole systems in SiGe devices Jungemann, C.
2013
84 C p. 112-119
8 p.
artikel
7 Disorder-induced variability of transport properties of sub-5 nm-wide graphene nanoribbons Poljak, M.
2013
84 C p. 103-111
9 p.
artikel
8 Drain-conductance optimization in nanowire TFETs by means of a physics-based analytical model Gnani, E.
2013
84 C p. 96-102
7 p.
artikel
9 Editorial Board 2013
84 C p. IFC-
1 p.
artikel
10 Flexible double gate a-IGZO TFT fabricated on free standing polyimide foil Münzenrieder, Niko
2013
84 C p. 198-204
7 p.
artikel
11 Foreword Zimmer, Thomas
2013
84 C p. 1-
1 p.
artikel
12 High performance printed N and P-type OTFTs enabling digital and analog complementary circuits on flexible plastic substrate Jacob, S.
2013
84 C p. 167-178
12 p.
artikel
13 Hot-electron conduction in ovonic materials Jacoboni, Carlo
2013
84 C p. 90-95
6 p.
artikel
14 Implication logic gates using spin-transfer-torque-operated magnetic tunnel junctions for intrinsic logic-in-memory Mahmoudi, Hiwa
2013
84 C p. 191-197
7 p.
artikel
15 In0.53Ga0.47As FinFETs with self-aligned molybdenum contacts and HfO2/Al2O3 gate dielectric Zhang, Xingui
2013
84 C p. 83-89
7 p.
artikel
16 Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks Ritzenthaler, R.
2013
84 C p. 22-27
6 p.
artikel
17 New parameter extraction method based on split C–V measurements in FDSOI MOSFETs Ben Akkez, Imed
2013
84 C p. 142-146
5 p.
artikel
18 80ns/45GHz Pulsed measurement system for DC and RF characterization of high speed microwave devices Weiß, Mario
2013
84 C p. 74-82
9 p.
artikel
19 On the impact of Ag doping on performance and reliability of GeS2-based conductive bridge memories Longnos, F.
2013
84 C p. 155-159
5 p.
artikel
20 Progress in Z2-FET 1T-DRAM: Retention time, writing modes, selective array operation, and dual bit storage Wan, Jing
2013
84 C p. 147-154
8 p.
artikel
21 Quasi-double gate regime to boost UTBB SOI MOSFET performance in analog and sleep transistor applications Kilchytska, V.
2013
84 C p. 28-37
10 p.
artikel
22 RTN and BTI in nanoscale MOSFETs: A comprehensive statistical simulation study Amoroso, Salvatore Maria
2013
84 C p. 120-126
7 p.
artikel
23 RTS noise characterization of HfO x RRAM in high resistive state Puglisi, Francesco M.
2013
84 C p. 160-166
7 p.
artikel
24 Scale changes in electronics: Implications for nanostructure devices for logic and memory and beyond Kim, Jaeyoon
2013
84 C p. 2-12
11 p.
artikel
25 Scaling of Trigate nanowire (NW) MOSFETs to sub-7nm width: 300K transition to Single Electron Transistor Deshpande, V.
2013
84 C p. 179-184
6 p.
artikel
26 Sensitivity-based investigation of threshold voltage variability in 32-nm flash memory cells and MOSFETs Bonfiglio, Valentina
2013
84 C p. 127-131
5 p.
artikel
27 Si tunneling transistors with high on-currents and slopes of 50mV/dec using segregation doped NiSi2 tunnel junctions Knoll, L.
2013
84 C p. 211-215
5 p.
artikel
28 Small NMR biomolecular sensors Sun, Nan
2013
84 C p. 13-21
9 p.
artikel
29 Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs Koyama, M.
2013
84 C p. 46-52
7 p.
artikel
30 Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance Alper, C.
2013
84 C p. 205-210
6 p.
artikel
31 Two-step annealing effects on ultrathin EOT higher-k (k =40) ALD-HfO2 gate stacks Morita, Yukinori
2013
84 C p. 58-64
7 p.
artikel
                             31 gevonden resultaten
 
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