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                             21 gevonden resultaten
nr titel auteur tijdschrift jaar jaarg. afl. pagina('s) type
1 A 60 GOPS/W, −1.8V to 0.9V body bias ULP cluster in 28nm UTBB FD-SOI technology Rossi, Davide
 2016
 117 C p. 170-184
15 p.
 artikel
2 A review of electrical characterization techniques for ultrathin FDSOI materials and devices Cristoloveanu, Sorin
 2016
 117 C p. 10-36
27 p.
 artikel
3 A review of special gate coupling effects in long-channel SOI MOSFETs with lightly doped ultra-thin bodies and their compact analytical modeling Rudenko, T.
 2016
 117 C p. 66-76
11 p.
 artikel
4 A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology Morin, Pierre
 2016
 117 C p. 100-116
17 p.
 artikel
5 Assessment of 28nm UTBB FD-SOI technology platform for RF applications: Figures of merit and effect of parasitic elements Kazemi Esfeh, B.
 2016
 117 C p. 130-137
8 p.
 artikel
6 A 1.36μW 312–315MHz synchronized-OOK receiver for wireless sensor networks using 65nm SOTB CMOS technology Hoang, Minh-Thien
 2016
 117 C p. 161-169
9 p.
 artikel
7 Body Bias usage in UTBB FDSOI designs: A parametric exploration approach Puschini, Diego
 2016
 117 C p. 138-145
8 p.
 artikel
8 Design and study of programmable ring oscillator using IDUDGMOSFET Mukherjee, Sagar
 2016
 117 C p. 193-198
6 p.
 artikel
9 Editorial Board 2016
 117 C p. IFC-
1 p.
 artikel
10 Effects of additional oxidation after Ge condensation on electrical properties of germanium-on-insulator p-channel MOSFETs Suh, Junkyo
 2016
 117 C p. 77-87
11 p.
 artikel
11 Electrical characterization of Random Telegraph Noise in Fully-Depleted Silicon-On-Insulator MOSFETs under extended temperature range and back-bias operation Marquez, Carlos
 2016
 117 C p. 60-65
6 p.
 artikel
12 Improving breakdown, conductive, and thermal performances for SOI high voltage LDMOS using a partial compound buried layer Hu, Shengdong
 2016
 117 C p. 146-151
6 p.
 artikel
13 Low frequency noise variability in ultra scaled FD-SOI n-MOSFETs: Dependence on gate bias, frequency and temperature Theodorou, C.G.
 2016
 117 C p. 88-93
6 p.
 artikel
14 Low voltage logic circuits exploiting gate level dynamic body biasing in 28nm UTBB FD-SOI Taco, Ramiro
 2016
 117 C p. 185-192
8 p.
 artikel
15 Mechanically flexible nanoscale silicon integrated circuits powered by photovoltaic energy harvesters Shahrjerdi, D.
 2016
 117 C p. 117-122
6 p.
 artikel
16 On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration de Souza, Michelly
 2016
 117 C p. 152-160
9 p.
 artikel
17 Planar Fully-Depleted-Silicon-On-Insulator technologies: Toward the 28nm node and beyond Doris, B.
 2016
 117 C p. 37-59
23 p.
 artikel
18 Special Issue: Planar Fully-Depleted SOI technology Allibert, F.
 2016
 117 C p. 1-
1 p.
 artikel
19 Temperature sensitivity analysis of dopingless charge-plasma transistor Shrivastava, Vishwas
 2016
 117 C p. 94-99
6 p.
 artikel
20 Ultra-thin body & buried oxide SOI substrate development and qualification for Fully Depleted SOI device with back bias capability Schwarzenbach, Walter
 2016
 117 C p. 2-9
8 p.
 artikel
21 Understanding and optimizing the floating body retention in FDSOI UTBOX Aoulaiche, M.
 2016
 117 C p. 123-129
7 p.
 artikel
                             21 gevonden resultaten
 
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