| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A Gated Clock Scheme for Low Power Testing of Logic Cores
|
Bonhomme, Yannick
|
|
2006
|
22 |
1 |
p. 89-99
|
artikel
|
| 2 |
An Efficient Dictionary Organization for Maximum Diagnosis
|
Chun, Sunghoon
|
|
2006
|
22 |
1 |
p. 37-48
|
artikel
|
| 3 |
A Self Test Program Design Technique for Embedded DSP Cores
|
Rizk, Hani
|
|
2006
|
22 |
1 |
p. 71-87
|
artikel
|
| 4 |
Automatic Test Pattern Generation for Resistive Bridging Faults
|
Engelke, Piet
|
|
2006
|
22 |
1 |
p. 61-69
|
artikel
|
| 5 |
Editorial
|
Agrawal, Vishwani D.
|
|
2006
|
22 |
1 |
p. 5
|
artikel
|
| 6 |
Modulo p = 3 Checking for a Carry Select Adder
|
Ocheretnij, V.
|
|
2006
|
22 |
1 |
p. 101-107
|
artikel
|
| 7 |
New JETTA Editors, 2006
|
Al-Hashimi, Bashir M.
|
|
2006
|
22 |
1 |
p. 9-10
|
artikel
|
| 8 |
Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic System Assembly
|
Shi, Zhen
|
|
2006
|
22 |
1 |
p. 49-60
|
artikel
|
| 9 |
Scaling of iDDT Test Methods for Random Logic Circuits
|
Chehab, Ali
|
|
2006
|
22 |
1 |
p. 11-22
|
artikel
|
| 10 |
Test Technology Newsletter
|
|
|
2006
|
22 |
1 |
p. 7-8
|
artikel
|
| 11 |
Theorems for Fault Collapsing in Combinational Circuits
|
Vaaje, Audhild
|
|
2006
|
22 |
1 |
p. 23-36
|
artikel
|
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