| no |
title |
author |
magazine |
year |
volume |
issue |
page(s) |
type |
| 1 |
A Discussion on Test Pattern Generation for FPGA—Implemented Circuits
|
Renovell, M.
|
|
2001
|
17 |
3-4 |
p. 283-290
|
article
|
| 2 |
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
|
Berthelot, D.
|
|
2001
|
17 |
3-4 |
p. 331-339
|
article
|
| 3 |
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
|
Hellebrand, Sybille
|
|
2001
|
17 |
3-4 |
p. 341-349
|
article
|
| 4 |
Application of Deterministic Logic BIST on Industrial Circuits
|
Kiefer, Gundolf
|
|
2001
|
17 |
3-4 |
p. 351-362
|
article
|
| 5 |
A System Level Boundary Scan Controller Board for VME Applications
|
Cardoso, Nuno
|
|
2001
|
17 |
3-4 |
p. 299-310
|
article
|
| 6 |
Compressed Bit Fail Maps for Memory Fail Pattern Classification
|
Vollrath, Jőrg
|
|
2001
|
17 |
3-4 |
p. 291-297
|
article
|
| 7 |
Current Testing Procedure for Deep Submicron Devices
|
Chichkov, Anton
|
|
2001
|
17 |
3-4 |
p. 219-224
|
article
|
| 8 |
Defect Detection from Visual Abnormalities in Manufacturing Process Using IDDQ
|
Sanada, Masaru
|
|
2001
|
17 |
3-4 |
p. 275-281
|
article
|
| 9 |
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences
|
Virazel, A.
|
|
2001
|
17 |
3-4 |
p. 233-241
|
article
|
| 10 |
Design for Delay Testability in High-Speed Digital ICs
|
Kerkhoff, H.G.
|
|
2001
|
17 |
3-4 |
p. 225-231
|
article
|
| 11 |
Editorial
|
Agrawal, Vishwani D.
|
|
2001
|
17 |
3-4 |
p. 203
|
article
|
| 12 |
Guest Editorial
|
Prinetto, Paolo
|
|
2001
|
17 |
3-4 |
p. 207
|
article
|
| 13 |
LEAP: An Accurate Defect-Free IDDQ Estimator
|
Ferré, Antoni
|
|
2001
|
17 |
3-4 |
p. 267-274
|
article
|
| 14 |
On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Reference Voltages
|
De Venuto, Daniela
|
|
2001
|
17 |
3-4 |
p. 243-253
|
article
|
| 15 |
Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST
|
Azaïs, F.
|
|
2001
|
17 |
3-4 |
p. 255-266
|
article
|
| 16 |
RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems
|
Santos, M.B.
|
|
2001
|
17 |
3-4 |
p. 311-319
|
article
|
| 17 |
Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach
|
Fummi, Franco
|
|
2001
|
17 |
3-4 |
p. 321-330
|
article
|
| 18 |
Test Challenges in Nanometer Technologies
|
Kundu, Sandip
|
|
2001
|
17 |
3-4 |
p. 209-218
|
article
|
| 19 |
Test Technology Technical Council Newsletter
|
|
|
2001
|
17 |
3-4 |
p. 205-206
|
article
|
Journal description