| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors
|
Chang, Ta-Chung
|
|
2000
|
16 |
1-2 |
p. 13-27
|
artikel
|
| 2 |
A Buffer-Oriented Methodology for Microarchitecture Validation
|
Utamaphethai, Noppanunt
|
|
2000
|
16 |
1-2 |
p. 49-65
|
artikel
|
| 3 |
An Efficient Logic Equivalence Checker for Industrial Circuits
|
Park, Jaehong
|
|
2000
|
16 |
1-2 |
p. 91-106
|
artikel
|
| 4 |
An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation
|
Shen, Jian
|
|
2000
|
16 |
1-2 |
p. 67-81
|
artikel
|
| 5 |
Automatic Vector Generation Using Constraints and Biasing
|
Yuan, Jun
|
|
2000
|
16 |
1-2 |
p. 107-120
|
artikel
|
| 6 |
Editorial
|
Agrawal, Vishwani D.
|
|
2000
|
16 |
1-2 |
p. 5
|
artikel
|
| 7 |
Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability
|
Seshadri, Sandhya
|
|
2000
|
16 |
1-2 |
p. 131-145
|
artikel
|
| 8 |
Guest Editorial
|
Abadir, Magdy
|
|
2000
|
16 |
1-2 |
p. 9-10
|
artikel
|
| 9 |
On Efficiently Producing Quality Tests for Custom Circuits in PowerPC™ Microprocessors
|
Wang, Li-C.
|
|
2000
|
16 |
1-2 |
p. 121-130
|
artikel
|
| 10 |
Oscillation Ring Delay Test for High Performance Microprocessors
|
Wu, Wen Ching
|
|
2000
|
16 |
1-2 |
p. 147-155
|
artikel
|
| 11 |
Testing for Function and Performance: Towards an Integrated Processor Validation Methodology
|
Bose, Pradip
|
|
2000
|
16 |
1-2 |
p. 29-48
|
artikel
|
| 12 |
Verification Simulation Acceleration Using Code-Perturbation
|
Min, Byeong
|
|
2000
|
16 |
1-2 |
p. 83-90
|
artikel
|
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