nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
1 |
A 10-bit dual-plate sampling DAC with capacitor reuse on-chip reference voltage generator
|
Gaddam, Ravi Shankar |
|
2013 |
44 |
6 |
p. 511-518 8 p. |
artikel |
2 |
Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells
|
Gupta, Kirti |
|
2013 |
44 |
6 |
p. 561-567 7 p. |
artikel |
3 |
Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level
|
Monteiro, Câncio |
|
2013 |
44 |
6 |
p. 496-503 8 p. |
artikel |
4 |
Completion detection in dual-rail asynchronous systems by current-sensing
|
Nagy, L. |
|
2013 |
44 |
6 |
p. 538-544 7 p. |
artikel |
5 |
Design and simulation of novel adder/subtractors on quantum-dot cellular automata: Radical departure from Boolean logic circuits
|
Gladshtein, Michael |
|
2013 |
44 |
6 |
p. 545-552 8 p. |
artikel |
6 |
Design and simulation of novel TLG–SET based RAM cell designs
|
Abutaleb, M.M. |
|
2013 |
44 |
6 |
p. 504-510 7 p. |
artikel |
7 |
Design of a compact reversible fault tolerant field programmable gate array: A novel approach in reversible logic synthesis
|
Shamsujjoha, Md. |
|
2013 |
44 |
6 |
p. 519-537 19 p. |
artikel |
8 |
Determining the reliable minimum unit capacitance for the DAC capacitor array of SAR ADCs
|
Yue, Xicai |
|
2013 |
44 |
6 |
p. 473-478 6 p. |
artikel |
9 |
Drain current model for a gate all around (GAA) p–n–p–n tunnel FET
|
Narang, Rakhi |
|
2013 |
44 |
6 |
p. 479-488 10 p. |
artikel |
10 |
Editorial board
|
|
|
2013 |
44 |
6 |
p. IFC- 1 p. |
artikel |
11 |
Low voltage dual mode logic: Model analysis and parameter extraction
|
Levi, I. |
|
2013 |
44 |
6 |
p. 553-560 8 p. |
artikel |
12 |
NORA based TDC in 90nm CMOS
|
Petra, N. |
|
2013 |
44 |
6 |
p. 489-495 7 p. |
artikel |