| no |
title |
author |
magazine |
year |
volume |
issue |
page(s) |
type |
| 1 |
A 10-bit dual-plate sampling DAC with capacitor reuse on-chip reference voltage generator
|
Gaddam, Ravi Shankar
|
|
|
44 |
6 |
p. 511-518
|
article
|
| 2 |
Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells
|
Gupta, Kirti
|
|
|
44 |
6 |
p. 561-567
|
article
|
| 3 |
Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level
|
Monteiro, Câncio
|
|
|
44 |
6 |
p. 496-503
|
article
|
| 4 |
Completion detection in dual-rail asynchronous systems by current-sensing
|
Nagy, L.
|
|
|
44 |
6 |
p. 538-544
|
article
|
| 5 |
Design and simulation of novel adder/subtractors on quantum-dot cellular automata: Radical departure from Boolean logic circuits
|
Gladshtein, Michael
|
|
|
44 |
6 |
p. 545-552
|
article
|
| 6 |
Design and simulation of novel TLG–SET based RAM cell designs
|
Abutaleb, M.M.
|
|
|
44 |
6 |
p. 504-510
|
article
|
| 7 |
Design of a compact reversible fault tolerant field programmable gate array: A novel approach in reversible logic synthesis
|
Shamsujjoha, Md.
|
|
|
44 |
6 |
p. 519-537
|
article
|
| 8 |
Determining the reliable minimum unit capacitance for the DAC capacitor array of SAR ADCs
|
Yue, Xicai
|
|
|
44 |
6 |
p. 473-478
|
article
|
| 9 |
Drain current model for a gate all around (GAA) p–n–p–n tunnel FET
|
Narang, Rakhi
|
|
|
44 |
6 |
p. 479-488
|
article
|
| 10 |
Editorial board
|
|
|
|
44 |
6 |
p. i
|
article
|
| 11 |
Low voltage dual mode logic: Model analysis and parameter extraction
|
Levi, I.
|
|
|
44 |
6 |
p. 553-560
|
article
|
| 12 |
NORA based TDC in 90nm CMOS
|
Petra, N.
|
|
|
44 |
6 |
p. 489-495
|
article
|
Journal description