| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A Fractional-N CP-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS
|
Jin, Zirui
|
|
|
132 |
C |
p.
|
artikel
|
| 2 |
A low-noise and mismatch-tolerant current-mirror-based potentiostat circuit for glucose monitoring
|
Nam, Kyeongsik
|
|
|
132 |
C |
p.
|
artikel
|
| 3 |
Analytical model for high-k SOI pLDMOS with self-adaptive balance of polarization charge
|
Wu, Lijuan
|
|
|
132 |
C |
p.
|
artikel
|
| 4 |
An ultralow specific on-resistance bidirectional trench power MOSFET with RESURF stepped oxide
|
Fang, Dong
|
|
|
132 |
C |
p.
|
artikel
|
| 5 |
A Sub-GHz multimode digital polar transmitter for 802.11ah and NB-IoT applications
|
Li, Tong
|
|
|
132 |
C |
p.
|
artikel
|
| 6 |
A 1T2M memristor-based logic circuit and its applications
|
Su, Bowen
|
|
|
132 |
C |
p.
|
artikel
|
| 7 |
Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design
|
Dai, Chenghu
|
|
|
132 |
C |
p.
|
artikel
|
| 8 |
Design of a high-performance router with distributed shared-buffer for load balancing for on-chip networks
|
Rezaei-Zare, Mina
|
|
|
132 |
C |
p.
|
artikel
|
| 9 |
Design of radiation-hardened memory cell by polar design for space applications
|
Hao, Licai
|
|
|
132 |
C |
p.
|
artikel
|
| 10 |
D-wash – A dynamic workload aware adaptive cache coherance protocol for multi-core processor system
|
Uma, V.
|
|
|
132 |
C |
p.
|
artikel
|
| 11 |
Editorial Board
|
|
|
|
132 |
C |
p.
|
artikel
|
| 12 |
Exact and approximate multiplications for signal processing applications
|
Patali, Pramod
|
|
|
132 |
C |
p.
|
artikel
|
| 13 |
MOSFET modeling of 0 . 18 μ m CMOS technology at 4.2K using BP neural network
|
Wang, Qiuwei
|
|
|
132 |
C |
p.
|
artikel
|
| 14 |
Single-event burnout hardening evaluation with current and electric field redistribution of high voltage LDMOS transistors based on TCAD Simulations
|
Lei, Yibo
|
|
|
132 |
C |
p.
|
artikel
|
| 15 |
SPARK: An automatic Score-Power-Area efficient RISC-V processor microarchitecture SeeKer
|
Li, Qiang
|
|
|
132 |
C |
p.
|
artikel
|
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