| no |
title |
author |
magazine |
year |
volume |
issue |
page(s) |
type |
| 1 |
A 2.6 GΩ, 1.4 μVrms current-reuse instrumentation amplifier for wearable electrocardiogram monitoring
|
Cao, Wenfei
|
|
|
107 |
C |
p.
|
article
|
| 2 |
A novel approach for the design of low-power pipelined synchronous systems operating in double–edge of the clock
|
Verducci Jr., Sir Orlando
|
|
|
107 |
C |
p.
|
article
|
| 3 |
An ultra-low-power CNFET based dual V DD ternary dynamic Half Adder
|
Vidhyadharan, Abhay S.
|
|
|
107 |
C |
p.
|
article
|
| 4 |
An ultra-low-power neural signal acquisition analog front-end IC
|
Tran, Luat
|
|
|
107 |
C |
p.
|
article
|
| 5 |
A wideband low power merged balance-balun-LNA and I/Q-mixer
|
Eskandari, R.
|
|
|
107 |
C |
p.
|
article
|
| 6 |
Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node
|
Vashishtha, Vinay
|
|
|
107 |
C |
p.
|
article
|
| 7 |
C3S–QVCO: A low phase noise low power super–harmonic coupling QVCO with cross–connected common–source nodes
|
Mazloum, Jalil
|
|
|
107 |
C |
p.
|
article
|
| 8 |
Design and simulation of ultra-low loss triple tapered asymmetric directional coupler at 1330 nm
|
Sharma, Bhawna
|
|
|
107 |
C |
p.
|
article
|
| 9 |
Design of a high linear and ultra-wideband LNA using post distortion star feedback method
|
Veisi, Siamak
|
|
|
107 |
C |
p.
|
article
|
| 10 |
Design of CMOS three-stage amplifiers for near-to-minimum settling-time
|
Giustolisi, Gianluca
|
|
|
107 |
C |
p.
|
article
|
| 11 |
Editorial Board
|
|
|
|
107 |
C |
p.
|
article
|
| 12 |
High speed RLC equivalent RC delay model using normalized asymptotic function for global VLSI interconnects
|
Jadav, Sunil
|
|
|
107 |
C |
p.
|
article
|
| 13 |
Statistical gate-delay modeling with copulas
|
Schneider, Walter
|
|
|
107 |
C |
p.
|
article
|
| 14 |
Voltage differencing buffered amplifier based low power, high frequency and universal filters using 32 nm CNTFET technology
|
Mamatov, Islombek
|
|
|
107 |
C |
p.
|
article
|
Journal description