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| Titel: |
Efficient Hardware Co-Simulation of Down Convertor for Wireless Communication Systems |
| Auteur: |
Rajesh Mehra Swapna Devi |
| Verschenen in: |
International journal of VLSI design & communication systems (VLSICS) |
| Paginering: | Jaargang 1 (2010) nr. 2 pagina's 13-21 |
| Jaar: |
2010 |
| Inhoud: |
In this paper an optimized hardware co-simulation approach is presented to design & implement GSMbased digital down convertor for Software Defined Radios. The proposed DDC is implemented usingoptimal equiripple technique to reduce the resource requirement. A computationally efficient polyphasedecomposition structure is used to improve the hardware complexity of the overall design. The proposedmodel is implemented by using embedded multipliers, LUTs and BRAMs of target device to enhance thesystem performance in terms of speed and area. The DDC model is designed and simulated with Simulinkand Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex-IIPro based xc2vp30-7ff896 FPGA device. The results show that proposed design can operate at maximumfrequency of 160 MHz by consuming power of 0.34004W 25 °C junction temperature. The proposeddesign is consuming very less resources available on target device to provide cost effective solution forSDR based wireless applications. |
| Uitgever: |
Academy & Industry Research Collaboration Center (AIRCC) (provided by DOAJ) |
| Bronbestand: |
Elektronische Wetenschappelijke Tijdschriften |
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