Design of Low Power Phase Locked Loop (PLL) Using 45NM VLSI Technology
Title:
Design of Low Power Phase Locked Loop (PLL) Using 45NM VLSI Technology
Author:
Ujwala A. Belorkar S.A.Ladhake
Appeared in:
International journal of VLSI design & communication systems (VLSICS)
Paging:
Volume 1 (2010) nr. 2 pages 1-11
Year:
2010
Contents:
Power has become one of the most important paradigms of design convergence for multigigahertz communication systems such as optical data links, wireless products, microprocessor &ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The coreof a microprocessor, which includes the largest power density on the microprocessor. In an effort toreduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction ofdynamic and static power consumption. Lowering the supply voltage, however, also reduces theperformance of the circuit, which is usually unacceptable. One way to overcome this limitation, availablein some application domains, is to replicate the circuit block whose supply voltage is being reduced inorder to maintain the same throughput .This paper introduces a design aspects for low power phaselocked loop using VLSI technology. This phase locked loop is designed using latest 45nm processtechnology parameters, which in turn offers high speed performance at low power. The main noveltyrelated to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnectdielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD, practical experience in layout design
Publisher:
Academy & Industry Research Collaboration Center (AIRCC) (provided by DOAJ)
Journal description