| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
Accelerating kernel classifiers through borders mapping
|
Mills, Peter
|
|
|
17 |
2 |
p. 313-327
|
artikel
|
| 2 |
All-hardware SIFT implementation for real-time VGA images feature extraction
|
Doménech-Asensi, Ginés
|
|
|
17 |
2 |
p. 371-382
|
artikel
|
| 3 |
An FPGA accelerator for PatchMatch multi-view stereo using OpenCL
|
Tatsumi, Shunsuke
|
|
|
17 |
2 |
p. 215-227
|
artikel
|
| 4 |
Efficient approximate core transform and its reconfigurable architectures for HEVC
|
Jridi, Maher
|
|
|
17 |
2 |
p. 329-339
|
artikel
|
| 5 |
Fast mode decision algorithm for HEVC intra coding based on texture partition and direction
|
Zhu, Wei
|
|
|
17 |
2 |
p. 275-292
|
artikel
|
| 6 |
FPGA Implementation of Optimized Karhunen–Loeve Transform for Image Processing Applications
|
Bhairannawar, Satish S.
|
|
|
17 |
2 |
p. 357-370
|
artikel
|
| 7 |
GMMSP on GPU
|
Ban, Zhihua
|
|
|
17 |
2 |
p. 245-257
|
artikel
|
| 8 |
Hierarchical prediction-based motion vector refinement for video frame-rate up-conversion
|
He, Jiale
|
|
|
17 |
2 |
p. 259-273
|
artikel
|
| 9 |
Image analyzer for stereoscopic camera rig alignment
|
Mielczarek, Aleksander
|
|
|
17 |
2 |
p. 383-391
|
artikel
|
| 10 |
In-loop perceptual model-based rate-distortion optimization for HEVC real-time encoder
|
Hu, Qiang
|
|
|
17 |
2 |
p. 293-311
|
artikel
|
| 11 |
Multi-level complexity reduction for HEVC multiview coding
|
Jiang, Caoyang
|
|
|
17 |
2 |
p. 197-213
|
artikel
|
| 12 |
Online action recognition from RGB-D cameras based on reduced basis decomposition
|
Arunraj, Muniandi
|
|
|
17 |
2 |
p. 341-356
|
artikel
|
| 13 |
Stereo vision architecture for heterogeneous systems-on-chip
|
Perri, Stefania
|
|
|
17 |
2 |
p. 393-415
|
artikel
|
| 14 |
Toward reliable experiments on the performance of Connected Components Labeling algorithms
|
Bolelli, Federico
|
|
|
17 |
2 |
p. 229-244
|
artikel
|
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