| no |
title |
author |
magazine |
year |
volume |
issue |
page(s) |
type |
| 1 |
A Clock Methodology for High-Performance Microprocessors
|
Carrig, Keith M.
|
|
1997
|
16 |
2-3 |
p. 217-224
|
article
|
| 2 |
Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations
|
Neves, Josè Luis
|
|
1997
|
16 |
2-3 |
p. 149-161
|
article
|
| 3 |
Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology
|
Hathaway, D.J.
|
|
1997
|
16 |
2-3 |
p. 191-198
|
article
|
| 4 |
Clock Distribution Methodology for PowerPC™ Microprocessors
|
Ganguly, Shantanu
|
|
1997
|
16 |
2-3 |
p. 181-189
|
article
|
| 5 |
Clocking Optimization and Distribution in Digital Systems with Scheduled Skews
|
Hsieh, Hong-Yean
|
|
1997
|
16 |
2-3 |
p. 131-147
|
article
|
| 6 |
Clock Skew Optimization for Peak Current Reduction
|
Benini, L.
|
|
1997
|
16 |
2-3 |
p. 117-130
|
article
|
| 7 |
High Performance Clock Distribution Networks
|
Friedman, Eby G.
|
|
1997
|
16 |
2-3 |
p. 113-116
|
article
|
| 8 |
Optical Clock Distribution in Electronic Systems
|
Tewksbury, Stuart K.
|
|
1997
|
16 |
2-3 |
p. 225-246
|
article
|
| 9 |
Practical Bounded-Skew Clock Routing
|
Kahng, Andrew B.
|
|
1997
|
16 |
2-3 |
p. 199-215
|
article
|
| 10 |
Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits
|
Gaj, Kris
|
|
1997
|
16 |
2-3 |
p. 247-276
|
article
|
| 11 |
Useful-Skew Clock Routing with Gate Sizing for Low Power Design
|
Xi, Joe Gufeng
|
|
1997
|
16 |
2-3 |
p. 163-179
|
article
|
Journal description