| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack
|
Dofe, Jaya
|
|
2016
|
32 |
5 |
p. 611-624
|
artikel
|
| 2 |
Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification
|
Lodhi, Faiq Khalid
|
|
2016
|
32 |
5 |
p. 569-586
|
artikel
|
| 3 |
A Novel Approach for Diagnosis of Analog Circuit Fault by Using GMKL-SVM and PSO
|
Zhang, Chaolong
|
|
2016
|
32 |
5 |
p. 531-540
|
artikel
|
| 4 |
A Novel Compact Model for On-Chip Vertically-Coiled Spiral Inductors
|
Hou, Bing
|
|
2016
|
32 |
5 |
p. 649-652
|
artikel
|
| 5 |
CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator
|
Yeh, Kuen-Wei
|
|
2016
|
32 |
5 |
p. 625-638
|
artikel
|
| 6 |
Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT
|
Kumar, T. Nandha
|
|
2016
|
32 |
5 |
p. 587-599
|
artikel
|
| 7 |
Editorial
|
Agrawal, Vishwani D.
|
|
2016
|
32 |
5 |
p. 505-506
|
artikel
|
| 8 |
Optimization of Test Wrapper for TSV Based 3D SOCs
|
Roy, Surajit Kumar
|
|
2016
|
32 |
5 |
p. 511-529
|
artikel
|
| 9 |
Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing
|
Shintani, Michihiro
|
|
2016
|
32 |
5 |
p. 601-609
|
artikel
|
| 10 |
Reliability Analysis of Fault-Tolerant Bus-Based Interconnection Networks
|
Bistouni, Fathollah
|
|
2016
|
32 |
5 |
p. 541-568
|
artikel
|
| 11 |
Test Data Compression for System-on-chip using Flexible Runs-aware PRL Coding
|
Yuan, Haiying
|
|
2016
|
32 |
5 |
p. 639-647
|
artikel
|
| 12 |
Test Technology Newsletter
|
|
|
2016
|
32 |
5 |
p. 507-509
|
artikel
|
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