| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic
|
Wu, Tie-Bin
|
|
2013
|
29 |
4 |
p. 585-600
|
artikel
|
| 2 |
A Fault Tolerant Hierarchical Network on Chip Router Architecture
|
Neishaburi, M. H.
|
|
2013
|
29 |
4 |
p. 485-497
|
artikel
|
| 3 |
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design
|
Thibeault, C.
|
|
2013
|
29 |
4 |
p. 457-471
|
artikel
|
| 4 |
An Approximate Calculation of Ratio of Normal Variables and Its Application in Analog Circuit Fault Diagnosis
|
Ao, Yongcai
|
|
2013
|
29 |
4 |
p. 555-565
|
artikel
|
| 5 |
Correlation of Heavy-Ion and Laser Testing on a DC/DC PWM Controller
|
Ren, Y.
|
|
2013
|
29 |
4 |
p. 609-616
|
artikel
|
| 6 |
Editorial
|
Agrawal, Vishwani D.
|
|
2013
|
29 |
4 |
p. 453
|
artikel
|
| 7 |
Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs
|
Schor, Lars
|
|
2013
|
29 |
4 |
p. 521-535
|
artikel
|
| 8 |
High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design
|
Niaraki Asli, Rahebeh
|
|
2013
|
29 |
4 |
p. 537-544
|
artikel
|
| 9 |
Memory Reliability Improvement Based on Maximized Error-Correcting Codes
|
Gherman, Valentin
|
|
2013
|
29 |
4 |
p. 601-608
|
artikel
|
| 10 |
Neural Network Guided Spatial Fault Resilience in Array Processors
|
Sindia, Suraj
|
|
2013
|
29 |
4 |
p. 473-483
|
artikel
|
| 11 |
Process-Variation and Temperature Aware SoC Test Scheduling Technique
|
Aghaee, Nima
|
|
2013
|
29 |
4 |
p. 499-520
|
artikel
|
| 12 |
Prognostics of Analog Filters Based on Particle Filters Using Frequency Features
|
Li, Min
|
|
2013
|
29 |
4 |
p. 567-584
|
artikel
|
| 13 |
Test Technology Newsletter
|
|
|
2013
|
29 |
4 |
p. 455-456
|
artikel
|
| 14 |
Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop
|
Namba, Kazuteru
|
|
2013
|
29 |
4 |
p. 545-554
|
artikel
|
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