nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
1 |
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors
|
Chang, Ta-Chung |
|
2000 |
|
1-2 |
p. 13-27 |
artikel |
2 |
A Bist Scheme for Non-Volatile Memories
|
Olivo, Piero |
|
1998 |
|
1-2 |
p. 139-144 |
artikel |
3 |
A Buffer-Oriented Methodology for Microarchitecture Validation
|
Utamaphethai, Noppanunt |
|
2000 |
|
1-2 |
p. 49-65 |
artikel |
4 |
Adaptive Fault Detection and Diagnosis of RAM Interconnects
|
Zhao, Jun |
|
1999 |
|
1-2 |
p. 157-171 |
artikel |
5 |
A Formalization of the IEEE 1149.1-1990 Diagnostic Methodology as Applied to Multichip Modules
|
Posse, Ken |
|
1997 |
|
1-2 |
p. 119-125 |
artikel |
6 |
A Low-Loss Built-In Current Sensor
|
Miura, Yukiya |
|
1999 |
|
1-2 |
p. 39-48 |
artikel |
7 |
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
|
Sogomonyan, E.S. |
|
1999 |
|
1-2 |
p. 87-96 |
artikel |
8 |
An Effective Multi-Chip BIST Scheme
|
Zorian, Yervant |
|
1997 |
|
1-2 |
p. 87-95 |
artikel |
9 |
An Efficient Logic Equivalence Checker for Industrial Circuits
|
Park, Jaehong |
|
2000 |
|
1-2 |
p. 91-106 |
artikel |
10 |
A New Design Method for Self-Checking Unidirectional Combinational Circuits
|
Saposhnikov, V.V. |
|
1998 |
|
1-2 |
p. 41-53 |
artikel |
11 |
An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation
|
Shen, Jian |
|
2000 |
|
1-2 |
p. 67-81 |
artikel |
12 |
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits
|
Girard, P. |
|
1999 |
|
1-2 |
p. 95-102 |
artikel |
13 |
A Survey of Test Techniques for MCM Substrates
|
Swaminathan, Madhavan |
|
1997 |
|
1-2 |
p. 27-38 |
artikel |
14 |
A Test Methodology for High Performance MCMs
|
Storey, Thomas M. |
|
1997 |
|
1-2 |
p. 109-118 |
artikel |
15 |
Automatic Vector Generation Using Constraints and Biasing
|
Yuan, Jun |
|
2000 |
|
1-2 |
p. 107-120 |
artikel |
16 |
BISTing Datapaths under Heterogeneous Test Schemes
|
Berthelot, D. |
|
1999 |
|
1-2 |
p. 115-123 |
artikel |
17 |
Characterization of Floating Gate Defects in Analog Cells
|
Brosa, Anna M. |
|
1999 |
|
1-2 |
p. 23-31 |
artikel |
18 |
Clocked Dosimeter Compatible with Digital CMOS Technology
|
Garcia-Moreno, E. |
|
1998 |
|
1-2 |
p. 101-110 |
artikel |
19 |
Concurrent Delay Testing in Totally Self-Checking Systems
|
Paschalis, Antonis |
|
1998 |
|
1-2 |
p. 55-61 |
artikel |
20 |
Decreasing the Sensitivity of ADC Test Parameters by Means of Wobbling
|
De Vries, R. |
|
1999 |
|
1-2 |
p. 23-29 |
artikel |
21 |
Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems
|
Gonçalves, F.M. |
|
1999 |
|
1-2 |
p. 41-52 |
artikel |
22 |
Delivering Dependable Telecommunication Services Using Off-the-Shelf System Components
|
Levendel, Y. |
|
1998 |
|
1-2 |
p. 153-159 |
artikel |
23 |
Design-For-Test in a Multiple Substrate Multichip Module
|
Jorgenson, Joel A. |
|
1997 |
|
1-2 |
p. 97-107 |
artikel |
24 |
Designing “Dual Personality” IEEE 1149.1 Compliant Multi-Chip Modules
|
Jarwala, Najmi |
|
1997 |
|
1-2 |
p. 77-86 |
artikel |
25 |
Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters
|
Piestrak, Stanislaw J. |
|
1998 |
|
1-2 |
p. 63-68 |
artikel |
26 |
Detection of Defects Using Fault Model Oriented Test Sequences
|
Renovell, M. |
|
1999 |
|
1-2 |
p. 13-22 |
artikel |
27 |
Deterministic BIST with Multiple Scan Chains
|
Kiefer, Gundolf |
|
1999 |
|
1-2 |
p. 85-93 |
artikel |
28 |
Deterministic Built-in Pattern Generation for Sequential Circuits
|
Iyengar, Vikram |
|
1999 |
|
1-2 |
p. 97-114 |
artikel |
29 |
Differential Thermal Testing: An Approach to its Feasibility
|
Altet, J. |
|
1999 |
|
1-2 |
p. 57-66 |
artikel |
30 |
Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die
|
Murphy, Cynthia F. |
|
1997 |
|
1-2 |
p. 151-166 |
artikel |
31 |
Editorial
|
Agrawal, Vishwani D. |
|
1999 |
|
1-2 |
p. 7 |
artikel |
32 |
Editorial
|
Agrawal, Vishwani D. |
|
1998 |
|
1-2 |
p. 5 |
artikel |
33 |
Editorial
|
Agrawal, Vishwani D. |
|
1997 |
|
1-2 |
p. 5 |
artikel |
34 |
Editorial
|
Agrawal, Vishwani D. |
|
2000 |
|
1-2 |
p. 5 |
artikel |
35 |
Editorial
|
Agrawal, Vishwani D. |
|
1999 |
|
1-2 |
p. 5 |
artikel |
36 |
Effect of Noise on Analog Circuit Testing
|
Iyer, Madhu K. |
|
1999 |
|
1-2 |
p. 11-22 |
artikel |
37 |
Efficient Path Selection for Delay Testing Based on Path Clustering
|
Tani, Seiichiro |
|
1999 |
|
1-2 |
p. 75-85 |
artikel |
38 |
Efficient Totally Self-Checking Shifter Design
|
Duarte, Ricardo O. |
|
1998 |
|
1-2 |
p. 29-39 |
artikel |
39 |
Electron Beam Probing—A Solution for MCM Test and Failure Analysis
|
Schmid, R. |
|
1997 |
|
1-2 |
p. 55-63 |
artikel |
40 |
Experience in Validation of PowerPCTM Microprocessor Embedded Arrays
|
Wang, Li-C. |
|
1999 |
|
1-2 |
p. 191-205 |
artikel |
41 |
Exploiting Behavioral Information in Gate-Level ATPG
|
Chiusano, Silvia |
|
1999 |
|
1-2 |
p. 141-148 |
artikel |
42 |
Fault-Tolerant Memory Architecture Against Radiation-Dependent Errors: A Mixed Error Control Approach
|
Mocanu, Octavian-Dumitru |
|
1999 |
|
1-2 |
p. 169-180 |
artikel |
43 |
Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability
|
Seshadri, Sandhya |
|
2000 |
|
1-2 |
p. 131-145 |
artikel |
44 |
From Design Validation to Hardware Testing: A Unified Approach
|
Al-Hayek, Ghassan |
|
1999 |
|
1-2 |
p. 133-140 |
artikel |
45 |
Fundamentals of MCM Testing and Design-for-Testability
|
Zorian, Yervant |
|
1997 |
|
1-2 |
p. 7-14 |
artikel |
46 |
Guest Editorial
|
Nicolaidis, Michael |
|
1999 |
|
1-2 |
p. 9 |
artikel |
47 |
Guest Editorial
|
Zorian, Yervant |
|
1997 |
|
1-2 |
p. 6 |
artikel |
48 |
Guest Editorial
|
Abadir, Magdy |
|
2000 |
|
1-2 |
p. 9-10 |
artikel |
49 |
Guest Editorial
|
Landrault, Christian |
|
1999 |
|
1-2 |
p. 11 |
artikel |
50 |
ICCQ: A Test Method for Analogue VLSI Using Local Current Sensors
|
Van Lammeren, Joop P.M. |
|
1999 |
|
1-2 |
p. 33-38 |
artikel |
51 |
IDDQ Testing of Opens in CMOS SRAMs
|
Champac, Victor H. |
|
1999 |
|
1-2 |
p. 53-62 |
artikel |
52 |
Incremental Testability Analysis for Partial Scan Selection and Design Transformations
|
Yang, Tianruo |
|
1999 |
|
1-2 |
p. 103-113 |
artikel |
53 |
Integrated Design and Test of Mixed-Signal Circuits
|
Engin, Nur |
|
1999 |
|
1-2 |
p. 75-83 |
artikel |
54 |
Integrated Temperature Sensors for On-Line Thermal Monitoring of Microelectronic Structures
|
Arabi, Karim |
|
1998 |
|
1-2 |
p. 93-99 |
artikel |
55 |
Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach
|
Feige, Chris |
|
1999 |
|
1-2 |
p. 125-131 |
artikel |
56 |
Known Good Die
|
Gilg, Larry |
|
1997 |
|
1-2 |
p. 15-25 |
artikel |
57 |
MCM Test Strategy Synthesis from Chip Test and Board Test Approaches
|
Flint, Andrew |
|
1997 |
|
1-2 |
p. 65-76 |
artikel |
58 |
Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures
|
Dias, Octávio P. |
|
1999 |
|
1-2 |
p. 149-158 |
artikel |
59 |
Mixed-Mode BIST Using Embedded Processors
|
Hellebrand, Sybille |
|
1998 |
|
1-2 |
p. 127-138 |
artikel |
60 |
Mixed Signal DFT at GHz Frequencies
|
Mason, R. |
|
1999 |
|
1-2 |
p. 31-39 |
artikel |
61 |
Multichip Module Diagnosis by Product-Code Signatures
|
Nagvajara, P. |
|
1997 |
|
1-2 |
p. 127-136 |
artikel |
62 |
New Techniques for Deterministic Test Pattern Generation
|
Hamzaoglu, Ilker |
|
1999 |
|
1-2 |
p. 63-73 |
artikel |
63 |
Off-Chip Diagnosis of Aperture Jitter in Full-Flash Analog-to-Digital Converters
|
Rosing, Richard |
|
1999 |
|
1-2 |
p. 67-74 |
artikel |
64 |
On Design Validation Using Verification Technology
|
Moundanos, Dinos |
|
1999 |
|
1-2 |
p. 173-189 |
artikel |
65 |
On Efficiently Producing Quality Tests for Custom Circuits in PowerPC™ Microprocessors
|
Wang, Li-C. |
|
2000 |
|
1-2 |
p. 121-130 |
artikel |
66 |
On-Line Fault Monitoring
|
Stiffler, J.J. |
|
1998 |
|
1-2 |
p. 21-27 |
artikel |
67 |
On-Line Fault Resilience Through Gracefully Degradable ASICs
|
Orailoğlu, Alex |
|
1998 |
|
1-2 |
p. 145-151 |
artikel |
68 |
On-Line Testing for VLSI—A Compendium of Approaches
|
Nicolaidis, M. |
|
1998 |
|
1-2 |
p. 7-20 |
artikel |
69 |
Oscillation Ring Delay Test for High Performance Microprocessors
|
Wu, Wen Ching |
|
2000 |
|
1-2 |
p. 147-155 |
artikel |
70 |
Quality Determination for Gate Delay Fault Tests Considering Three-State Elements
|
Pöhl, Frank |
|
1999 |
|
1-2 |
p. 49-55 |
artikel |
71 |
Scalable Test Generators for High-Speed Datapath Circuits
|
Al-Asaad, Hussain |
|
1998 |
|
1-2 |
p. 111-125 |
artikel |
72 |
Self-Testing Embedded Two-Rail Checkers
|
Nikolos, Dimitris |
|
1998 |
|
1-2 |
p. 69-79 |
artikel |
73 |
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test
|
García, T.A. |
|
1999 |
|
1-2 |
p. 115-127 |
artikel |
74 |
Simulation Techniques for the Manufacturing Test of MCMs
|
Tegethoff, Mick |
|
1997 |
|
1-2 |
p. 137-149 |
artikel |
75 |
Smart Substrate MCMs
|
Gattiker, Anne E. |
|
1997 |
|
1-2 |
p. 39-53 |
artikel |
76 |
SRAM-Based FPGAs: Testing the Embedded RAM Modules
|
Renovell, M. |
|
1999 |
|
1-2 |
p. 159-167 |
artikel |
77 |
Structural Fault Testing of Embedded Cores Using Pipelining
|
Nourani, M. |
|
1999 |
|
1-2 |
p. 129-144 |
artikel |
78 |
Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
|
Das, Debaleena |
|
1999 |
|
1-2 |
p. 145-155 |
artikel |
79 |
Testing for Function and Performance: Towards an Integrated Processor Validation Methodology
|
Bose, Pradip |
|
2000 |
|
1-2 |
p. 29-48 |
artikel |
80 |
Test Technology Technical Council Newsletter
|
|
|
1999 |
|
1-2 |
p. 7-8 |
artikel |
81 |
Thermal Monitoring of Self-Checking Systems
|
Székely, V. |
|
1998 |
|
1-2 |
p. 81-92 |
artikel |
82 |
Verification Simulation Acceleration Using Code-Perturbation
|
Min, Byeong |
|
2000 |
|
1-2 |
p. 83-90 |
artikel |