| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A Balanced Capacitive Threshold-Logic Gate
|
Javier López-García
|
|
2004
|
40 |
1 |
p. 61-69
9 p.
|
artikel
|
| 2 |
A Balanced Capacitive Threshold-Logic Gate
|
López-García, Javier
|
|
2004
|
40 |
1 |
p. 61-69
|
artikel
|
| 3 |
A CAD-Based Investigation of Clock-Skew Hazards in Pipelined NORA Dynamic Logic Circuits
|
Fei Yuan
|
|
2004
|
40 |
1 |
p. 103-108
6 p.
|
artikel
|
| 4 |
A CAD-Based Investigation of Clock-Skew Hazards in Pipelined NORA Dynamic Logic Circuits
|
Yuan, Fei
|
|
2004
|
40 |
1 |
p. 103-108
|
artikel
|
| 5 |
A Four Quadrant Analog Multiplier Employing Single CDBA
|
Ali Ümit Keskin
|
|
2004
|
40 |
1 |
p. 99-101
3 p.
|
artikel
|
| 6 |
A Four Quadrant Analog Multiplier Employing Single CDBA
|
Keskin, Ali Ümit
|
|
2004
|
40 |
1 |
p. 99-101
|
artikel
|
| 7 |
A New CMOS Rail-to-Rail Low Distortion Balanced Output Transconductor
|
Mohamed A. Youssef
|
|
2004
|
40 |
1 |
p. 75-82
8 p.
|
artikel
|
| 8 |
A New CMOS Rail-to-Rail Low Distortion Balanced Output Transconductor
|
Youssef, Mohamed A.
|
|
2004
|
40 |
1 |
p. 75-82
|
artikel
|
| 9 |
A Rank Encoder Adaptive Analog to Digital Conversion Exploiting Time Domain Spike Signal Processing
|
Philipp Häfliger
|
|
2004
|
40 |
1 |
p. 39-51
13 p.
|
artikel
|
| 10 |
A Rank Encoder: Adaptive Analog to Digital Conversion Exploiting Time Domain Spike Signal Processing
|
Häfliger, Philipp
|
|
2004
|
40 |
1 |
p. 39-51
|
artikel
|
| 11 |
A Square-Root Domain Differentiator Circuit
|
Spiridon Vlassis
|
|
2004
|
40 |
1 |
p. 53-59
7 p.
|
artikel
|
| 12 |
A Square-Root Domain Differentiator Circuit
|
Vlassis, Spiridon
|
|
2004
|
40 |
1 |
p. 53-59
|
artikel
|
| 13 |
A Wide Bandwidth Isolation Amplifier Design Using Current Conveyors
|
An Sang Hou
|
|
2004
|
40 |
1 |
p. 31-38
8 p.
|
artikel
|
| 14 |
A Wide Bandwidth Isolation Amplifier Design Using Current Conveyors
|
Hou, An Sang
|
|
2004
|
40 |
1 |
p. 31-38
|
artikel
|
| 15 |
Common-Mode Response Overlapping vs. Shaping in Rail-to-Rail Op-Amp Input Stages
|
J. Francisco Duque-Carrillo
|
|
2004
|
40 |
1 |
p. 21-29
9 p.
|
artikel
|
| 16 |
Common-Mode Response Overlapping vs. Shaping in Rail-to-Rail Op-Amp Input Stages
|
Duque-Carrillo, J. Francisco
|
|
2004
|
40 |
1 |
p. 21-29
|
artikel
|
| 17 |
Interconnect Macromodelling and Approximation of Matrix Exponent
|
V.G. Kurbatov
|
|
2004
|
40 |
1 |
p. 5-19
15 p.
|
artikel
|
| 18 |
Interconnect Macromodelling and Approximation of Matrix Exponent
|
Kurbatov, V.G.
|
|
2004
|
40 |
1 |
p. 5-19
|
artikel
|
| 19 |
New Wide Band Low Power CMOS Current Conveyors
|
Wessam S. Hassanein
|
|
2004
|
40 |
1 |
p. 91-97
7 p.
|
artikel
|
| 20 |
New Wide Band Low Power CMOS Current Conveyors
|
Hassanein, Wessam S.
|
|
2004
|
40 |
1 |
p. 91-97
|
artikel
|
| 21 |
Novel Canonic Current Mode DDCC Based SRCO Synthesized Using a Genetic Algorithm
|
Varun Aggarwal
|
|
2004
|
40 |
1 |
p. 83-85
3 p.
|
artikel
|
| 22 |
Novel Canonic Current Mode DDCC Based SRCO Synthesized Using a Genetic Algorithm
|
Aggarwal, Varun
|
|
2004
|
40 |
1 |
p. 83-85
|
artikel
|
| 23 |
SITO High Output Impedance Transadmittance Filter Using FTFNs
|
N.A. Shah
|
|
2004
|
40 |
1 |
p. 87-89
3 p.
|
artikel
|
| 24 |
SITO High Output Impedance Transadmittance Filter Using FTFNs
|
Shah, N.A.
|
|
2004
|
40 |
1 |
p. 87-89
|
artikel
|
| 25 |
Very Low Voltage MOS Translinear Loops Based on Flipped Voltage Followers
|
Antonio J. López-Martín
|
|
2004
|
40 |
1 |
p. 71-74
4 p.
|
artikel
|
| 26 |
Very Low Voltage MOS Translinear Loops Based on Flipped Voltage Followers
|
López-Martín, Antonio J.
|
|
2004
|
40 |
1 |
p. 71-74
|
artikel
|
Tijdschrift beschrijving