| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A 12-bit branching time-to-digital converter with power saving features and digital based resolution tuning for PVT variations
|
Teh, Jian Sen
|
|
|
105 |
1 |
p. 57-71
|
artikel
|
| 2 |
A 1.8 GHz temperature drift compensated LC-VCO for RFID transceiver
|
Liu, Qingshan
|
|
|
105 |
1 |
p. 7-12
|
artikel
|
| 3 |
Analysis and investigation of CDBA based fractional-order filters
|
Kaur, Gagandeep
|
|
|
105 |
1 |
p. 111-124
|
artikel
|
| 4 |
Analysis of oscillator phase noise effect on high order QAM links
|
Bicici, Cagri
|
|
|
105 |
1 |
p. 1-6
|
artikel
|
| 5 |
An opamp-free second-order noise-shaping SAR ADC with 4× passive gain using capacitive charge pump
|
Yi, Pinyun
|
|
|
105 |
1 |
p. 125-133
|
artikel
|
| 6 |
A reusable stage based reduced comparator count binary search ADC
|
Dipti,
|
|
|
105 |
1 |
p. 33-43
|
artikel
|
| 7 |
A self-adaptive pulse generator to realize extremely low power consumption and high reliability of high voltage gate driver IC
|
Yu, Siyuan
|
|
|
105 |
1 |
p. 13-20
|
artikel
|
| 8 |
Energy efficient switching scheme based on MSB-split structure for SAR ADC
|
Han, Shanshan
|
|
|
105 |
1 |
p. 135-139
|
artikel
|
| 9 |
Least squares linear phase FIR filter design and its VLSI implementation
|
Khan, Mansoor
|
|
|
105 |
1 |
p. 99-109
|
artikel
|
| 10 |
Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current
|
Díaz-Madrid, José Ángel
|
|
|
105 |
1 |
p. 45-55
|
artikel
|
| 11 |
Open-loop digital clock generator based VLSI architecture for electromagnetic interference reduction
|
Meenakshi Vidya, P.
|
|
|
105 |
1 |
p. 21-32
|
artikel
|
| 12 |
SBOX under PVT variation
|
Kumar, Abhishek
|
|
|
105 |
1 |
p. 73-82
|
artikel
|
| 13 |
Variation-tolerant, low-power, and high endurance read scheme for memristor memories
|
Ravi, V.
|
|
|
105 |
1 |
p. 83-98
|
artikel
|
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