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                             130 results found
no title author magazine year volume issue page(s) type
1 A behavioral approach to testability analysis for neural networks Piuri, Vincenzo
1992
35 1-5 p. 181-186
6 p.
article
2 A chip set implementation of a parallel cellular architecture Gregoretti, F.
1992
35 1-5 p. 417-425
9 p.
article
3 A clause indexing unit for prolog Renaux, Douglas
1992
35 1-5 p. 311-318
8 p.
article
4 A comparative analysis of cache memory architectures for the MULTIPLUS multiprocessor Meslin, Alexandre Malheiros
1992
35 1-5 p. 555-562
8 p.
article
5 A comparison study of minimization methods of unit interconnection in VLIW processors Carriere, C.
1992
35 1-5 p. 595-602
8 p.
article
6 A data driven hybrid computer architecture Tseng, Chien-Chao
1992
35 1-5 p. 89-96
8 p.
article
7 A high level synthesis algorithm including control constraints Verdier, François
1992
35 1-5 p. 271-278
8 p.
article
8 A hybrid knowledge-based approach to information retrieval Yoon, Yongun
1992
35 1-5 p. 329-336
8 p.
article
9 A light weight kernel server Stainov, Rumen
1992
35 1-5 p. 39-45
7 p.
article
10 Allocation of precedence-constrained tasks to parallel processors for optimal execution Das, Rina
1992
35 1-5 p. 237-244
8 p.
article
11 A low cost solution for HDTV data reduction Steckenbiller, Helmut
1992
35 1-5 p. 611-618
8 p.
article
12 A multi-processor shared memory architecture for parallel cyclic reference counting Lius, Rafael D.
1992
35 1-5 p. 563-568
6 p.
article
13 An abstract prolog machine based on parallel resolution principle Vlahavas, I.
1992
35 1-5 p. 755-762
8 p.
article
14 An adaptable frame multiplexing scheme for source routing bridges Antonakopoulos, T.
1992
35 1-5 p. 409-416
8 p.
article
15 An approach to testability analysis and improvement for VLSI systems Gu, Xinli
1992
35 1-5 p. 485-492
8 p.
article
16 A new magnitude function for fast numbers comparison in the residue number system Dimauro, G.
1992
35 1-5 p. 97-104
8 p.
article
17 An integrated access control in heterogeneous distributed database systems Kang, Sukhoon
1992
35 1-5 p. 429-436
8 p.
article
18 An interactive environment for the model-based design of analog circuits Hoffmann, Klaus
1992
35 1-5 p. 79-85
7 p.
article
19 An object-oriented approach to High-Level Petri Nets Camurri, Antonio
1992
35 1-5 p. 213-220
8 p.
article
20 A pearl-based multi-loop and multi-sequence controller Welter, R.
1992
35 1-5 p. 707-712
6 p.
article
21 Application machines: An approach to realizing understandable systems Lawson, Harold W.
1992
35 1-5 p. 5-10
6 p.
article
22 A quadratic programming approach to estimatingthe testability and coverage distributions of a VLSI circuit Farhat, H.
1992
35 1-5 p. 479-483
5 p.
article
23 A reconfigurable boolean n-cube architecture under faults Yang, C.S.
1992
35 1-5 p. 673-679
7 p.
article
24 Artificial neural network realization with programmable logic circuit Guštin, Veselko
1992
35 1-5 p. 187-192
6 p.
article
25 A self-tuning robust fuzzy controller Nowe, Ann
1992
35 1-5 p. 719-726
8 p.
article
26 A software architecture for sound and music processing Camurri, Antonio
1992
35 1-5 p. 625-632
8 p.
article
27 A software generator for multi-transputer-based real-time applications Pasquier, O.
1992
35 1-5 p. 529-536
8 p.
article
28 A transputer network for a device simulator Boittiaux, B.
1992
35 1-5 p. 127-132
6 p.
article
29 A trip to object-oriented land Ancona, M.
1992
35 1-5 p. 195-202
8 p.
article
30 A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port Royals, Mark
1992
35 1-5 p. 493-500
8 p.
article
31 Author index to volume 35 (1992) 1992
35 1-5 p. 803-806
4 p.
article
32 Automated implementations of Lotos specification Cuypers, Ludo
1992
35 1-5 p. 729-735
7 p.
article
33 Chairman's introduction Jutand, Francis
1992
35 1-5 p. vii-
1 p.
article
34 Checkpointing and recovery in a pipeline of transputers Sinha, A.
1992
35 1-5 p. 141-147
7 p.
article
35 Circuit yield optimization by analyzing performance statistics Graeb, Helmut E.
1992
35 1-5 p. 697-703
7 p.
article
36 CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents Hübner, U.
1992
35 1-5 p. 377-382
6 p.
article
37 Communicating active components: An environment for concurrent applications on parallel machines Courtrai, Luc
1992
35 1-5 p. 47-54
8 p.
article
38 Complement 1992
35 1-5 p. 115-116
2 p.
article
39 Construction of large-size interconnection networks with high performance Shen, Hong
1992
35 1-5 p. 545-554
10 p.
article
40 Constructive evaluation of computer architectures: A CAD approach Michl, R.
1992
35 1-5 p. 571-578
8 p.
article
41 Contrasting instruction-fetch time and instruction-decode time branch prediction mechanisms: Achieving synergy through their cooperative operation Kaeli, David R.
1992
35 1-5 p. 401-408
8 p.
article
42 Data layouts impacts on the compilation of the communications for a synchronous MSIMD machine Delaplace, F.
1992
35 1-5 p. 469-475
7 p.
article
43 DELTA-T: A user-transparent software-monitoring tool for multi-transputer systems Maehle, Erik
1992
35 1-5 p. 245-252
8 p.
article
44 Dependence graph transformations in the design of processor arrays for matrix multiplications Wyrzykowski, Roman
1992
35 1-5 p. 539-544
6 p.
article
45 Deriving protocol specifications from service specifications including multirendezvous Kapus-Kolar, Monika
1992
35 1-5 p. 369-374
6 p.
article
46 Design of a DSP-based discrete variable structure controller with improved robustness Leung, Nixon C.M.
1992
35 1-5 p. 713-717
5 p.
article
47 Design of the processing node of the PTAH 64 parallel computer Cappello, F.
1992
35 1-5 p. 105-111
7 p.
article
48 Development of a real-time database management system for production process-control applications Lee, Heonguil
1992
35 1-5 p. 445-452
8 p.
article
49 Digital system simulation with VHDL in a high-level synthesis system Peng, Zebo
1992
35 1-5 p. 263-269
7 p.
article
50 Editorial Board 1992
35 1-5 p. IFC-
1 p.
article
51 Efficient implementation of regular parallel adders for binary signed digit number representations Zehendner, Eberhard
1992
35 1-5 p. 319-326
8 p.
article
52 Enhancing the fuzzy set model for high quality document rankings Lee, Joon Ho
1992
35 1-5 p. 337-344
8 p.
article
53 EPVD: An interactive protocol specification and validation environment in Estelle formal specification Huang, K.C.
1992
35 1-5 p. 71-77
7 p.
article
54 Estimators for logic minimization and implementation selection of finite state machines ten Berg, A.J.W.M.
1992
35 1-5 p. 151-158
8 p.
article
55 ETS - a performance prediction tool for protocols specified in FDT Estelle Chlamtac, I.
1992
35 1-5 p. 651-658
8 p.
article
56 Fault diagnosis for the generalized Boolean n-cube network Huang, T.C.
1992
35 1-5 p. 661-665
5 p.
article
57 Fault tolerant wormhole routing in hypercube multicomputers Yang, C.S.
1992
35 1-5 p. 667-672
6 p.
article
58 From image coding to multimedia: Algorithms and architectures for a revolution Demassieux, Nicolas
1992
35 1-5 p. 3-
1 p.
article
59 From specification to implementation of a real-time system Carcagno, L.
1992
35 1-5 p. 737-744
8 p.
article
60 Galatea neural VLSI architectures: Communication and control considerations Alippi, Cesare
1992
35 1-5 p. 175-180
6 p.
article
61 Highest performance computing machines Patt, Y.N.
1992
35 1-5 p. 1-
1 p.
article
62 High-level synthesis Pawlak, Adam
1992
35 1-5 p. 261-
1 p.
article
63 Implementation of statecharts with transputers Calvez, J.P.
1992
35 1-5 p. 133-139
7 p.
article
64 Improving the probabilistic clock synchronization algorithm Alari, Gianluigi
1992
35 1-5 p. 463-467
5 p.
article
65 Intel i860 versus Digital Signal Processors (DSP) Silberg, Steen
1992
35 1-5 p. 605-610
6 p.
article
66 IPTES — Incremental Prototyping Technology for Embedded real-time Systems Pulli, Petri
1992
35 1-5 p. 13-21
9 p.
article
67 LEFT — A learning tool for early floorplanning Herrmann, Jürgen
1992
35 1-5 p. 587-594
8 p.
article
68 Level-2 cache for high performance /390 μ-processors Barsuhn, H.
1992
35 1-5 p. 303-309
7 p.
article
69 Making specifications executable — Using IPTES Meta-IV Andersen, Michael
1992
35 1-5 p. 521-528
8 p.
article
70 Measuring and analyzing real-time kernel performance Berggren, Hans
1992
35 1-5 p. 635-640
6 p.
article
71 Measuring and simulating an 802.3 CSMA/CD LAN van Oorschot, Jan
1992
35 1-5 p. 765-772
8 p.
article
72 Modelling of digital circuits function and functional faults on register transfer level Gawin, Jacek
1992
35 1-5 p. 167-172
6 p.
article
73 MPPNL — A Petri Net based Language to design fine-grained parallel machines and debug their software Pissaloux, Edwige E.
1992
35 1-5 p. 231-236
6 p.
article
74 Multiple input transitions in CMOS gates Melcher, Elmar
1992
35 1-5 p. 683-690
8 p.
article
75 Neural network implementations and speed-up on Massively Parallel machines Azema-Barac, M.E.
1992
35 1-5 p. 747-754
8 p.
article
76 Object-oriented analysis and modeling with the ESAstation Schaschinger, Harald
1992
35 1-5 p. 221-227
7 p.
article
77 Object-oriented versus conventional software development: A comparative case study Pree, W
1992
35 1-5 p. 203-211
9 p.
article
78 On the design of a highly testable cell library Saraiva, M.
1992
35 1-5 p. 383-389
7 p.
article
79 On the use of OR-BDDs for test generation Jóźwiak, Lech
1992
35 1-5 p. 159-166
8 p.
article
80 Performance comparison of signature-based multikey access methods Chang, Jae Woo
1992
35 1-5 p. 345-352
8 p.
article
81 Performance evaluation: An analytical model for calculating start misses in caches Kolarz, T.
1992
35 1-5 p. 297-302
6 p.
article
82 Power consumption estimation using statistical signal properties Roethig, Wolfgang
1992
35 1-5 p. 691-696
6 p.
article
83 Program chairman's introduction Graff Mortensen, Benny
1992
35 1-5 p. ix-
1 p.
article
84 Program Committee 1992
35 1-5 p. xi-xii
nvt p.
article
85 PROOFS: Application engineering based on formal methods van Hee, Kees
1992
35 1-5 p. 29-36
8 p.
article
86 PTD: Architectural system description support based on visual specification languages Sánchez Allende, Jesús
1992
35 1-5 p. 513-520
8 p.
article
87 Results of the esprit basic research action 3148 demon (design methods based on nets) Best, Eike
1992
35 1-5 p. 23-27
5 p.
article
88 Reviewers 1992
35 1-5 p. xiii-xiv
nvt p.
article
89 Segmentation of echocardiograms using a neural network Sun, Yung-Nien
1992
35 1-5 p. 791-798
8 p.
article
90 Session A1: Esprit/Race I 1992
35 1-5 p. 11-12
2 p.
article
91 Session A4: Processor design 1992
35 1-5 p. 87-
1 p.
article
92 Session A3: Specification and design 1992
35 1-5 p. 61-
1 p.
article
93 Session B1: Esprit/Race II 1992
35 1-5 p. 113-114
2 p.
article
94 Session B4: Neural networks 1992
35 1-5 p. 173-
1 p.
article
95 Session B2: Transputer Applications 1992
35 1-5 p. 125-
1 p.
article
96 Session C1: Advances in object-oriented design 1992
35 1-5 p. 193-
1 p.
article
97 Session C4: Arithmetic and memory organization 1992
35 1-5 p. 295-
1 p.
article
98 Session chairpersons 1992
35 1-5 p. xv-
1 p.
article
99 Session chairperson's addresses 1992
35 1-5 p. 799-801
3 p.
article
100 Session D4: Control methods 1992
35 1-5 p. 399-
1 p.
article
101 Session D3: Design for testability I 1992
35 1-5 p. 375-376
2 p.
article
102 Session E1: Database systems 1992
35 1-5 p. 427-428
2 p.
article
103 Session E3: Design for testability II 1992
35 1-5 p. 477-
1 p.
article
104 Session F1: Development environments 1992
35 1-5 p. 503-
1 p.
article
105 Session F4: Digital signal processing 1992
35 1-5 p. 603-
1 p.
article
106 Session F2: Parallel architectures I Pissaloux, E.E.
1992
35 1-5 p. 537-538
2 p.
article
107 Session G4: Control algorithms and applications 1992
35 1-5 p. 705-
1 p.
article
108 Session G2: Fault tolerant networks 1992
35 1-5 p. 659-
1 p.
article
109 Session G1: Verification and validation 1992
35 1-5 p. 633-634
2 p.
article
110 Session H1: From specification to implementation 1992
35 1-5 p. 727-
1 p.
article
111 Session H4: Neural network sensor processing 1992
35 1-5 p. 781-
1 p.
article
112 Session H2: Parallel architectures II 1992
35 1-5 p. 745-746
2 p.
article
113 Silicon compilation and rapid prototyping of microprogrammed VLSI-Circuits with MIMOLA and SOLO 1400 Hendrich, N.
1992
35 1-5 p. 287-294
8 p.
article
114 SIMPAC-T : A simulator for multitransputer systems Arunkumar, S.
1992
35 1-5 p. 253-260
8 p.
article
115 Sound recognition and optimal neural network design Refenes, A.N.
1992
35 1-5 p. 783-789
7 p.
article
116 Specification and design of concurrent control units Klein-Hessling, G.
1992
35 1-5 p. 63-70
8 p.
article
117 SPECS: Formal methods and techniques for telecommunications software development Dauphin, Michel
1992
35 1-5 p. 117-124
8 p.
article
118 State assignment and testability of PLA-based finite state machines Buonanno, Giacomo
1992
35 1-5 p. 391-398
8 p.
article
119 Stochastic modelling of a high speed, short packet length, slotted ring with finite queueing capacity Woodward, Michael E.
1992
35 1-5 p. 773-779
7 p.
article
120 Subject index to volume 35 1992
35 1-5 p. 807-809
3 p.
article
121 Systematic synthesis of parallel VLSI architectures from FP specifications and its application to scene matching Tsanakas, Panayotis
1992
35 1-5 p. 579-586
8 p.
article
122 System performance modeling with functional schemes and VHDL Bakowski, P.
1992
35 1-5 p. 279-285
7 p.
article
123 Task level specification and communication Benders, L.P.M.
1992
35 1-5 p. 355-362
8 p.
article
124 The dining philosophers problem and its decentralisation Vaughan, John G.
1992
35 1-5 p. 455-462
8 p.
article
125 The specification and design of atomic actions for fault tolerant concurrent software Tyrrell, A.M.
1992
35 1-5 p. 363-368
6 p.
article
126 Transaction management for global serializability and local autonomy in multidatabase systems Hwang, Buhyun
1992
35 1-5 p. 437-444
8 p.
article
127 Transputer model of the human peripheral hearing system Tyrrell, Andrew M.
1992
35 1-5 p. 619-624
6 p.
article
128 TriOS operating system Jerebic, Izidor
1992
35 1-5 p. 55-60
6 p.
article
129 UISER - a customizable software engineering environment for development-in-the-large Laine, Antti
1992
35 1-5 p. 505-512
8 p.
article
130 Verifying networks of processes that communicate via shared variables Kapus, Tatjana
1992
35 1-5 p. 641-649
9 p.
article
                             130 results found
 
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