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                             22 gevonden resultaten
nr titel auteur tijdschrift jaar jaarg. afl. pagina('s) type
1 A BiNoC architecture—aware task allocation and communication scheduling scheme Tsai, Wen-Chung
 2016
 42 C p. 215-226
12 p.
 artikel
2 A fair energy resource allocation strategy for micro grid Chao, Hung-Lin
 2016
 42 C p. 235-244
10 p.
 artikel
3 A low-area dynamic reconfigurable MDC FFT processor design Lee, Trong-Yen
 2016
 42 C p. 227-234
8 p.
 artikel
4 Analysis of network-on-chip topologies for cost-efficient chip multiprocessors Ortín-Obón, Marta
 2016
 42 C p. 24-36
13 p.
 artikel
5 An FPGA stereo matching unit based on fuzzy logic Pérez-Patricio, M.
 2016
 42 C p. 87-99
13 p.
 artikel
6 A processor for IoT applications: An assessment of design space and trade-offs Johann, Sergio F.
 2016
 42 C p. 156-164
9 p.
 artikel
7 Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration Cheng, Wei-Kai
 2016
 42 C p. 191-199
9 p.
 artikel
8 Combining the parabolic synthesis methodology with second-degree interpolation Hertz, Erik
 2016
 42 C p. 142-155
14 p.
 artikel
9 Component-based design of cyber-physical applications with safety-critical requirements Masrur, Alejandro
 2016
 42 C p. 70-86
17 p.
 artikel
10 Computational architectures for sonar array processing in autonomous rovers Mishra, Prabhakar
 2016
 42 C p. 49-69
21 p.
 artikel
11 Design and verification of Cyber-Physical Systems using TrueTime, evolutionary optimization and UPPAAL Balasubramaniyan, Sreram
 2016
 42 C p. 37-48
12 p.
 artikel
12 Editorial Board 2016
 42 C p. iii-
1 p.
 artikel
13 Editorial Board / Aims and Scope 2016
 42 C p. IFC-
1 p.
 artikel
14 Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches Gong, Young-Ho
 2016
 42 C p. 100-112
13 p.
 artikel
15 Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor Azarpeyvand, Ali
 2016
 42 C p. 113-126
14 p.
 artikel
16 Higher security of ASIC fabrication process against reverse engineering attack using automatic netlist encryption methodology Zamanzadeh, S.
 2016
 42 C p. 1-9
9 p.
 artikel
17 Introduction to the special issue on smart reconfigurable system modeling, design, and implementation Hsiung, Pao-Ann
 2016
 42 C p. 190-
1 p.
 artikel
18 Novel low power reversible binary incrementer design using quantum-dot cellular automata Das, Jadav Chandra
 2016
 42 C p. 10-23
14 p.
 artikel
19 Pipelining data-dependent tasks in FPGA-based multicore architectures Azarian, Ali
 2016
 42 C p. 165-179
15 p.
 artikel
20 Protection of heterogeneous architectures on FPGAs: An approach based on hardware firewalls Cotret, Pascal
 2016
 42 C p. 127-141
15 p.
 artikel
21 Reconfigurable cache for real-time MPSoCs: Scheduling and implementation Chen, Gang
 2016
 42 C p. 200-214
15 p.
 artikel
22 Reconfigurable multicast routing for Networks on Chip Nasiri, Fatemeh
 2016
 42 C p. 180-189
10 p.
 artikel
                             22 gevonden resultaten
 
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