| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A delay-locked loop with self-calibration circuit for reducing phase error
|
Kao, Shao-ku
|
|
|
44 |
8 |
p. 663-669
|
artikel
|
| 2 |
A highly linear squarer design for energy-detection RF receivers
|
Yargholi, Mostafa
|
|
|
44 |
8 |
p. 658-662
|
artikel
|
| 3 |
A high o/p resistance, wide swing and perfect current matching charge pump having switching circuit for PLL
|
Hati, Manas Kumar
|
|
|
44 |
8 |
p. 649-657
|
artikel
|
| 4 |
A multiple frequency clock generator using wide operation frequency range phase interpolator
|
Yang, Wei-Bin
|
|
|
44 |
8 |
p. 688-695
|
artikel
|
| 5 |
Data bus swizzling in TSV-based three-dimensional integrated circuits
|
Ge, Shen
|
|
|
44 |
8 |
p. 696-705
|
artikel
|
| 6 |
Editorial board
|
|
|
|
44 |
8 |
p. i
|
artikel
|
| 7 |
Fast optimization of nano-CMOS voltage-controlled oscillator using polynomial regression and genetic algorithm
|
Ghai, Dhruva
|
|
|
44 |
8 |
p. 631-641
|
artikel
|
| 8 |
Low-voltage bulk-driven rectifier for biomedical applications
|
Khateb, Fabian
|
|
|
44 |
8 |
p. 642-648
|
artikel
|
| 9 |
Parallel architecture for DNA sequence inexact matching with Burrows-Wheeler Transform
|
Xin, Yao
|
|
|
44 |
8 |
p. 670-682
|
artikel
|
| 10 |
Reconfigurable gate array architecture for logic functions in tunneling transistor technology
|
Gerousis, C.
|
|
|
44 |
8 |
p. 706-711
|
artikel
|
| 11 |
Single capacitor with current amplifier compensation for ultra-large capacitive load three-stage amplifier
|
Liao, Pengfei
|
|
|
44 |
8 |
p. 712-717
|
artikel
|
| 12 |
Single-ended, robust 8T SRAM cell for low-voltage operation
|
Wen, Liang
|
|
|
44 |
8 |
p. 718-728
|
artikel
|
| 13 |
Split compensation for inverter-based two-stage amplifier
|
Liao, Pengfei
|
|
|
44 |
8 |
p. 683-687
|
artikel
|
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