| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A fast general slew constrained minimum cost buffering algorithm
|
Hu, Shiyan
|
|
|
40 |
10 |
p. 1482-1486
|
artikel
|
| 2 |
A fully redundant decimal adder and its application in parallel decimal multipliers
|
Gorgin, Saeid
|
|
|
40 |
10 |
p. 1471-1481
|
artikel
|
| 3 |
A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter
|
Navi, K.
|
|
|
40 |
10 |
p. 1441-1448
|
artikel
|
| 4 |
A 30pA/V– 25 μ A / V linear CMOS channel-length-modulation OTA
|
Huang, Yan
|
|
|
40 |
10 |
p. 1458-1465
|
artikel
|
| 5 |
A systematic design approach for low-power 10-bit 100MS/s pipelined ADC
|
Meganathan, D.
|
|
|
40 |
10 |
p. 1417-1435
|
artikel
|
| 6 |
A wide dynamic range CMOS image sensor with pulse-frequency-modulation and in-pixel amplification
|
Chen, Yong
|
|
|
40 |
10 |
p. 1496-1501
|
artikel
|
| 7 |
CMOS voltage-mode quaternary look-up tables for multi-valued FPGAs
|
da Silva, R.C.G.
|
|
|
40 |
10 |
p. 1466-1470
|
artikel
|
| 8 |
Design-for-testability techniques for CORDIC design
|
Ye, Bo-Yuan
|
|
|
40 |
10 |
p. 1436-1440
|
artikel
|
| 9 |
Editorial board
|
|
|
|
40 |
10 |
p. i
|
artikel
|
| 10 |
FIR filter optimization using bit-edge equalization in high-speed backplane data transmission
|
Zhang, Lei
|
|
|
40 |
10 |
p. 1449-1457
|
artikel
|
| 11 |
Low-power and high-performance techniques in global interconnect signaling
|
Moghaddam Tabrizi, Mohammad
|
|
|
40 |
10 |
p. 1487-1495
|
artikel
|
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