| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
Active memory chips: a brief survey and case study
|
|
|
|
18 |
6 |
p. 53
|
artikel
|
| 2 |
A 256-kbit flash E2PROM using triple-polysilicon technology
|
|
|
|
18 |
6 |
p. 54
|
artikel
|
| 3 |
An easily testable optimal-time VLSI-multiplier B Becker (Univ. des Saarlandes, Saarbrucken, Germany)
|
|
|
|
18 |
6 |
p. 52
|
artikel
|
| 4 |
A systolic signal processor for signal-processing applications
|
|
|
|
18 |
6 |
p. 52
|
artikel
|
| 5 |
A testable design of programmable logic arrays with universal control and minimal overhead
|
|
|
|
18 |
6 |
p. 51
|
artikel
|
| 6 |
Bipolar GaAs gate arrays set new performance levels
|
|
|
|
18 |
6 |
p. 53
|
artikel
|
| 7 |
Book review
|
Shute, M.J.
|
|
|
18 |
6 |
p. 58
|
artikel
|
| 8 |
Control static-column DRAM with improved logic array
|
|
|
|
18 |
6 |
p. 53
|
artikel
|
| 9 |
Editorial
|
Butcher, John
|
|
|
18 |
6 |
p. 3
|
artikel
|
| 10 |
Effectiveness of single fault tests to detect multiple faults in parity trees
|
|
|
|
18 |
6 |
p. 51
|
artikel
|
| 11 |
Explicit formulation of delays in CMOS VLSI
|
|
|
|
18 |
6 |
p. 52
|
artikel
|
| 12 |
Fast and dense low-power multiple-valued I2L circuit
|
|
|
|
18 |
6 |
p. 53
|
artikel
|
| 13 |
Forthcoming events
|
|
|
|
18 |
6 |
p. 61-64
|
artikel
|
| 14 |
Hot electron effects in narrow width MOS devices
|
Petrova, R.S.
|
|
|
18 |
6 |
p. 25-30
|
artikel
|
| 15 |
Is the incoming physical inspection of microelectronic components really necessary?
|
Richards, B.P.
|
|
|
18 |
6 |
p. 4-24
|
artikel
|
| 16 |
Megabit dynamic RAMs target system solutions
|
|
|
|
18 |
6 |
p. 54
|
artikel
|
| 17 |
Memory supervision with the M68000 processor. II. Realisation with the PMMU component
|
|
|
|
18 |
6 |
p. 54
|
artikel
|
| 18 |
Parliamentary report
|
|
|
|
18 |
6 |
p. 55-57
|
artikel
|
| 19 |
Partitioning: an essential step in mapping algorithms into systolic array processors
|
|
|
|
18 |
6 |
p. 52
|
artikel
|
| 20 |
Polymer thick film systems and surface mount techniques
|
Cousens, A.K.
|
|
|
18 |
6 |
p. 50
|
artikel
|
| 21 |
Programmable logic device preserves pins, product terms
|
|
|
|
18 |
6 |
p. 53
|
artikel
|
| 22 |
Research and Development
|
|
|
|
18 |
6 |
p. 59-60
|
artikel
|
| 23 |
Role of composite materials in a functional approach to miniaturisation in electronics
|
Satyam, M.
|
|
|
18 |
6 |
p. 40-48
|
artikel
|
| 24 |
Simulation of resist profiles in single and triple layer electron beam lithography
|
Deshmukh, P.R.
|
|
|
18 |
6 |
p. 32-38
|
artikel
|
| 25 |
SLAPP: a systolic linear algebra parallel processor
|
|
|
|
18 |
6 |
p. 52
|
artikel
|
| 26 |
Some systolic array developments in the United Kingdom
|
|
|
|
18 |
6 |
p. 52
|
artikel
|
| 27 |
Testing in two-dimensional iterative logic arrays
|
|
|
|
18 |
6 |
p. 51
|
artikel
|
| 28 |
The design of a GaAs systolic array for an adaptive null steering beamforming controller
|
|
|
|
18 |
6 |
p. 52
|
artikel
|
| 29 |
Two processors to one memory. Dual-port-DRAM-controller controls access
|
|
|
|
18 |
6 |
p. 54
|
artikel
|
| 30 |
Wavefront array processors-concept to implementation
|
|
|
|
18 |
6 |
p. 52
|
artikel
|
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