| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array
|
Dong, Li
|
|
|
113 |
C |
p.
|
artikel
|
| 2 |
A compact QRS detection system based on 0.79 μW analog CMOS energy-of-derivative circuit
|
Silva, Rafael Sanchotene
|
|
|
113 |
C |
p.
|
artikel
|
| 3 |
A fanout-improved Parallel Prefix Adder with full-swing PTL cells and Graded Bit Efficiency
|
Rahimi, M.
|
|
|
113 |
C |
p.
|
artikel
|
| 4 |
A 25 Gbps inductorless optical receiver analog front-end based the modified Cherry-Hooper amplifier for optical interconnect
|
Zhou, Gaolei
|
|
|
113 |
C |
p.
|
artikel
|
| 5 |
A 20-Gb/s charge-steering equalizer utilizing highly-efficient charge-steering linear equalizer
|
Saif, Marco A.
|
|
|
113 |
C |
p.
|
artikel
|
| 6 |
A 24 GHz PLL with low phase noise for 60 GHz Sliding-IF transceiver in a 65-nm CMOS
|
Liu, Yang
|
|
|
113 |
C |
p.
|
artikel
|
| 7 |
A 2.4 GHz receiver with a current-reused inductor-less noise-canceling balun LNA in 40 nm CMOS
|
Liu, Xiaoming
|
|
|
113 |
C |
p.
|
artikel
|
| 8 |
A multiple-sensitivity Hall sensor featuring a low-cost temperature compensation circuit
|
Mo, Shaoqing
|
|
|
113 |
C |
p.
|
artikel
|
| 9 |
A novel control circuit for piezoelectric energy harvesting
|
Zhang, Zhang
|
|
|
113 |
C |
p.
|
artikel
|
| 10 |
A novel design for voltage inverting metamutator and its applications
|
Arundeepakvel, R
|
|
|
113 |
C |
p.
|
artikel
|
| 11 |
A 2.1 ppm/°C, 0.55–2.4 V, 5.6 nW, 235 mV, CMOS-only subthreshold voltage reference
|
Duan, Quanzhen
|
|
|
113 |
C |
p.
|
artikel
|
| 12 |
A single-inductor thermoelectric and photovoltaic hybrid harvesting interface with time-multiplexed technology and accurate zero current detector
|
Liu, Lianxi
|
|
|
113 |
C |
p.
|
artikel
|
| 13 |
Broadband linearity enhancement method for a 1.3 GHz–2.5 GHz digitally-assisted oscillator in a 55-nm CMOS technology
|
Fang, Yun
|
|
|
113 |
C |
p.
|
artikel
|
| 14 |
CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic
|
Mahboob Sardroudi, Farzin
|
|
|
113 |
C |
p.
|
artikel
|
| 15 |
CNTFET design of a multiple-port ternary register file
|
Mohammaden, Amr
|
|
|
113 |
C |
p.
|
artikel
|
| 16 |
Column amplification stages in CMOS image sensors based on incremental sigma-delta ADCs
|
Freitas, Luis Miguel C.
|
|
|
113 |
C |
p.
|
artikel
|
| 17 |
Design of integrated laser diode driver for 3D-depth sensing applications
|
David, Romain
|
|
|
113 |
C |
p.
|
artikel
|
| 18 |
Design of 0.8V, 22 nm DG-FinFET based efficient VLSI multiplexers
|
Jeevan, B.
|
|
|
113 |
C |
p.
|
artikel
|
| 19 |
Editorial Board
|
|
|
|
113 |
C |
p.
|
artikel
|
| 20 |
Efficient butterfly inspired optimization algorithm for analog circuits design
|
Lberni, Abdelaziz
|
|
|
113 |
C |
p.
|
artikel
|
| 21 |
Half-select disturb-free single-ended 9-transistor SRAM cell with bit-interleaving scheme in TMDFET technology
|
Izadinasab, Farzaneh
|
|
|
113 |
C |
p.
|
artikel
|
| 22 |
High-performance quaternary latch and D-Type flip-flop with selective outputs
|
Safipoor, Fatemeh
|
|
|
113 |
C |
p.
|
artikel
|
| 23 |
High-throughput configurable SIMON architecture for flexible security
|
Sheikhpour, Saeideh
|
|
|
113 |
C |
p.
|
artikel
|
| 24 |
Impact of temperature and interface trapped charges variation on the Analog/RF and linearity of vertically extended drain double gate Si 0.5 Ge 0.5 source tunnel FET
|
Kumari, Pallavi
|
|
|
113 |
C |
p.
|
artikel
|
| 25 |
Low voltage high performance super class AB OTA design using SCCM and DTMOS with enhanced slew rate and DC gain
|
Mahendra, Mihika
|
|
|
113 |
C |
p.
|
artikel
|
| 26 |
Modeling of line impedance stabilization network impedance characteristic based on genetic algorithm
|
Zhu, Zhibo
|
|
|
113 |
C |
p.
|
artikel
|
| 27 |
Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs
|
Kumar, Nitish
|
|
|
113 |
C |
p.
|
artikel
|
| 28 |
Organic/amorphous silicon hybrid tandem solar cell with PDPP3T as organic active layer
|
Liu, X.
|
|
|
113 |
C |
p.
|
artikel
|
| 29 |
Predicting the impact of transient voltage suppressor used for ESD protection on the low noise amplifier
|
Mengxia, Zhou
|
|
|
113 |
C |
p.
|
artikel
|
| 30 |
Simulation study on ferroelectric layer thickness dependence RF/Analog and linearity parameters in ferroelectric tunnel junction TFET
|
Saha, Rajesh
|
|
|
113 |
C |
p.
|
artikel
|
| 31 |
Ultra low power current mirror design with enhanced bandwidth
|
Pritty,
|
|
|
113 |
C |
p.
|
artikel
|
| 32 |
Ultra low-power negative DC voltage generator based on a proposed level shifter and voltage reference
|
Rezaei, Neda
|
|
|
113 |
C |
p.
|
artikel
|
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