| no |
title |
author |
magazine |
year |
volume |
issue |
page(s) |
type |
| 1 |
Advances in Wafer Level Packaging (WLP)
|
Tee, Tong Yan
|
|
2010
|
50 |
4 |
p. 479-480
2 p.
|
article
|
| 2 |
Calendar
|
|
|
2010
|
50 |
4 |
p. I-III
nvt p.
|
article
|
| 3 |
Design and optimization of thermo-mechanical reliability in wafer level packaging
|
Fan, X.J.
|
|
2010
|
50 |
4 |
p. 536-546
11 p.
|
article
|
| 4 |
Designing for reliability using a new Wafer Level Package structure
|
Hochstenbach, P.H.
|
|
2010
|
50 |
4 |
p. 528-535
8 p.
|
article
|
| 5 |
Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection
|
Shen, Li-Cheng
|
|
2010
|
50 |
4 |
p. 489-497
9 p.
|
article
|
| 6 |
Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package
|
Sze, Theresa
|
|
2010
|
50 |
4 |
p. 498-506
9 p.
|
article
|
| 7 |
Editorial
|
Vanzi, Massimo
|
|
2010
|
50 |
4 |
p. 455-
1 p.
|
article
|
| 8 |
Finite element modeling on electromigration of solder joints in wafer level packages
|
Dandu, P.
|
|
2010
|
50 |
4 |
p. 547-555
9 p.
|
article
|
| 9 |
Forward-stepwise regression analysis for fine leak batch testing of wafer-level hermetic MEMS packages
|
Jang, Changsoo
|
|
2010
|
50 |
4 |
p. 507-513
7 p.
|
article
|
| 10 |
Geometric design for ultra-long needle probe card for digital light processing wafer testing
|
Chang, Hao-Yuan
|
|
2010
|
50 |
4 |
p. 556-563
8 p.
|
article
|
| 11 |
Inside front cover - Editorial board
|
|
|
2010
|
50 |
4 |
p. IFC-
1 p.
|
article
|
| 12 |
Multiple impact characterization of wafer level packaging (WLP)
|
Crosbie, Paul
|
|
2010
|
50 |
4 |
p. 577-582
6 p.
|
article
|
| 13 |
New methodology for the assessment of the thermal resistance of laser diodes and light emitting diodes
|
Veyrié, David
|
|
2010
|
50 |
4 |
p. 456-461
6 p.
|
article
|
| 14 |
Rate-dependent properties of Sn–Ag–Cu based lead-free solder joints for WLCSP
|
Su, Y.A.
|
|
2010
|
50 |
4 |
p. 564-576
13 p.
|
article
|
| 15 |
Redistribution in wafer level chip size packaging technology for high power device applications: Process and design considerations
|
Chen, Jiunn
|
|
2010
|
50 |
4 |
p. 522-527
6 p.
|
article
|
| 16 |
Reliability evaluation for Blu-Ray laser diodes
|
Meneghini, Matteo
|
|
2010
|
50 |
4 |
p. 467-470
4 p.
|
article
|
| 17 |
Strain estimation in III–V materials by analysis of the degree of polarization of luminescence
|
Cassidy, Daniel T.
|
|
2010
|
50 |
4 |
p. 462-466
5 p.
|
article
|
| 18 |
The interpretation of the DC characteristics of LED and laser diodes to address their failure analysis
|
Mura, G.
|
|
2010
|
50 |
4 |
p. 471-478
8 p.
|
article
|
| 19 |
Trends of power semiconductor wafer level packaging
|
Liu, Yong
|
|
2010
|
50 |
4 |
p. 514-521
8 p.
|
article
|
| 20 |
Wafer-level bonding/stacking technology for 3D integration
|
Ko, Cheng-Ta
|
|
2010
|
50 |
4 |
p. 481-488
8 p.
|
article
|
Journal description