nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
1 |
An ESD test reduction method for complex devices
|
Maksimovic, Dejan |
|
2009 |
49 |
12 |
p. 1465-1469 5 p. |
artikel |
2 |
A new compact model for external latchup
|
Farbiz, Farzan |
|
2009 |
49 |
12 |
p. 1447-1454 8 p. |
artikel |
3 |
A plug-and-play wideband RF circuit ESD protection methodology: T-diodes
|
Linten, D. |
|
2009 |
49 |
12 |
p. 1440-1446 7 p. |
artikel |
4 |
Assessment of acceleration models used for BGA solder joint reliability studies
|
Yang, Liyu |
|
2009 |
49 |
12 |
p. 1546-1554 9 p. |
artikel |
5 |
Calendar
|
|
|
2009 |
49 |
12 |
p. I-II nvt p. |
artikel |
6 |
CDM tests on interface test chips for the verification of ESD protection concepts
|
Brodbeck, Tilo |
|
2009 |
49 |
12 |
p. 1470-1475 6 p. |
artikel |
7 |
Characterization of the transient behavior of gated/STI diodes and their associated BJT in the CDM time domain
|
Manouvrier, Jean-Robert |
|
2009 |
49 |
12 |
p. 1424-1432 9 p. |
artikel |
8 |
Classification of high-voltage varistors into groups of differentiated quality
|
Hasse, Lech |
|
2009 |
49 |
12 |
p. 1483-1490 8 p. |
artikel |
9 |
Corrosion-induced degradation of GaAs PHEMTs under operation in high humidity conditions
|
Hisaka, Takayuki |
|
2009 |
49 |
12 |
p. 1515-1519 5 p. |
artikel |
10 |
Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits
|
Kshirsagar, R.V. |
|
2009 |
49 |
12 |
p. 1573-1577 5 p. |
artikel |
11 |
Design optimization of gate-silicided ESD NMOSFETs in a 45nm bulk CMOS technology
|
Alvarez, David |
|
2009 |
49 |
12 |
p. 1417-1423 7 p. |
artikel |
12 |
Dielectric thinning model applied to metal insulator metal capacitors with Al2O3 dielectric
|
Allers, K.H. |
|
2009 |
49 |
12 |
p. 1520-1528 9 p. |
artikel |
13 |
Editorial ESD reliability special section
|
Vassilev, Vesselin |
|
2009 |
49 |
12 |
p. 1405-1406 2 p. |
artikel |
14 |
ESD robust high-voltage active clamps
|
Notermans, Guido |
|
2009 |
49 |
12 |
p. 1433-1439 7 p. |
artikel |
15 |
Evaluate the orderings of risk for failure problems using a more general RPN methodology
|
Chang, Kuei-Hu |
|
2009 |
49 |
12 |
p. 1586-1596 11 p. |
artikel |
16 |
Experimental study of filling behaviors in the underfill encapsulation of a flip-chip
|
Shih, Meng-Fu |
|
2009 |
49 |
12 |
p. 1555-1562 8 p. |
artikel |
17 |
Failure rate estimation of known failure mechanisms of electronic packages
|
Yang, Liyu |
|
2009 |
49 |
12 |
p. 1563-1572 10 p. |
artikel |
18 |
Fast and stable computation of optical propagation in micro-waveguides with loss
|
Zhu, Jianxin |
|
2009 |
49 |
12 |
p. 1529-1536 8 p. |
artikel |
19 |
Functional delay test generation based on software prototype
|
Bareisa, Eduardas |
|
2009 |
49 |
12 |
p. 1578-1585 8 p. |
artikel |
20 |
Inside front cover - Editorial board
|
|
|
2009 |
49 |
12 |
p. IFC- 1 p. |
artikel |
21 |
Investigating the CDM susceptibility of IC’s at package and wafer level by capacitive coupled TLP
|
Wolf, Heinrich |
|
2009 |
49 |
12 |
p. 1476-1481 6 p. |
artikel |
22 |
Investigation of novel attributes of single halo dual-material double gate MOSFETs for analog/RF applications
|
Mohankumar, N. |
|
2009 |
49 |
12 |
p. 1491-1497 7 p. |
artikel |
23 |
Modeling of hetero-interface potential and threshold voltage for tied and separate nanoscale InAlAs–InGaAs symmetric double-gate HEMT
|
Rathi, Servin |
|
2009 |
49 |
12 |
p. 1508-1514 7 p. |
artikel |
24 |
NBTI model development with regression analysis
|
Katsetos, Anastasios A. |
|
2009 |
49 |
12 |
p. 1498-1502 5 p. |
artikel |
25 |
Optimal placement of electronic devices in forced convective cooling conditions
|
Felczak, M. |
|
2009 |
49 |
12 |
p. 1537-1545 9 p. |
artikel |
26 |
Reliability aspects of gate oxide under ESD pulse stress
|
Ille, Adrien |
|
2009 |
49 |
12 |
p. 1407-1416 10 p. |
artikel |
27 |
Stability of the J–V characteristics of (BEHP-PPV)-co-(MEH-PPV) based light-emitting diodes
|
Sánchez, J.C. |
|
2009 |
49 |
12 |
p. 1503-1507 5 p. |
artikel |
28 |
Transient interferometric mapping of carrier plasma during external transient latch-up phenomena in latch-up test structures and I/O cells processed in CMOS technology
|
Heer, Michael |
|
2009 |
49 |
12 |
p. 1455-1464 10 p. |
artikel |