| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
Ag metallization with high electromigration resistance for ULSI
|
Hauder, M
|
|
2003
|
47 |
7 |
p. 1227-1231
5 p.
|
artikel
|
| 2 |
A new model for the current factor mismatch in the MOS transistor
|
Difrenza, R.
|
|
2003
|
47 |
7 |
p. 1167-1171
5 p.
|
artikel
|
| 3 |
Characterization of effective mobility by split C(V) technique in N-MOSFETs with ultra-thin gate oxides
|
Lime, F
|
|
2003
|
47 |
7 |
p. 1147-1153
7 p.
|
artikel
|
| 4 |
Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime
|
Luyken, R.J.
|
|
2003
|
47 |
7 |
p. 1199-1203
5 p.
|
artikel
|
| 5 |
Electrical characterization of copper interconnects with end-of-roadmap feature sizes
|
Schindler, G
|
|
2003
|
47 |
7 |
p. 1233-1236
4 p.
|
artikel
|
| 6 |
Evaluation of circuit performance of ultra-thin-body SOI CMOS
|
Pacha, Christian
|
|
2003
|
47 |
7 |
p. 1205-1211
7 p.
|
artikel
|
| 7 |
Fabrication of Schottky barrier MOSFETs on SOI by a self-assembly CoSi2-patterning method
|
Zhao, Qing-Tai
|
|
2003
|
47 |
7 |
p. 1183-1186
4 p.
|
artikel
|
| 8 |
High frequency n-type MODFETs on ultra-thin virtual SiGe substrates
|
Hackbarth, T
|
|
2003
|
47 |
7 |
p. 1179-1182
4 p.
|
artikel
|
| 9 |
High performance Si/SiGe pMOSFETs fabricated in a standard CMOS process technology
|
Collaert, N
|
|
2003
|
47 |
7 |
p. 1173-1177
5 p.
|
artikel
|
| 10 |
Impact of parasitic elements on the performance of digital CMOS circuits with Gigabit feature size
|
Schwantes, Stefan
|
|
2003
|
47 |
7 |
p. 1243-1248
6 p.
|
artikel
|
| 11 |
[No title]
|
Risch, Lothar
|
|
2003
|
47 |
7 |
p. 1131-
1 p.
|
artikel
|
| 12 |
Processing technology for the investigation of sub-50 nm copper damascene interconnects
|
Steinlesberger, G
|
|
2003
|
47 |
7 |
p. 1237-1241
5 p.
|
artikel
|
| 13 |
Quantum corrections in the simulation of decanano MOSFETs
|
Asenov, A.
|
|
2003
|
47 |
7 |
p. 1141-1145
5 p.
|
artikel
|
| 14 |
Shrinking from 0.25 down to 0.12 μm SOI CMOS technology node: a contribution to low-frequency noise in partially depleted N-MOSFETs
|
Dieudonné, F
|
|
2003
|
47 |
7 |
p. 1213-1218
6 p.
|
artikel
|
| 15 |
Simulation and optimization of EJ-MOSFETs
|
Kittler, M.
|
|
2003
|
47 |
7 |
p. 1193-1198
6 p.
|
artikel
|
| 16 |
Simulation of the Esaki-tunneling FET
|
Wang, Peng-Fei
|
|
2003
|
47 |
7 |
p. 1187-1192
6 p.
|
artikel
|
| 17 |
Static and low frequency noise characterization in surface- and buried-mode 0.1 μm PMOSFETS
|
Fadlallah, M.
|
|
2003
|
47 |
7 |
p. 1155-1160
6 p.
|
artikel
|
| 18 |
Strained Si CMOS (SS CMOS) technology: opportunities and challenges
|
Rim, K.
|
|
2003
|
47 |
7 |
p. 1133-1139
7 p.
|
artikel
|
| 19 |
The impact of short channel and quantum effects on the MOS transistor mismatch
|
Difrenza, R
|
|
2003
|
47 |
7 |
p. 1161-1165
5 p.
|
artikel
|
| 20 |
Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOI devices
|
Munteanu, D.
|
|
2003
|
47 |
7 |
p. 1219-1225
7 p.
|
artikel
|
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