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                                       Details for article 7 of 8 found articles
 
 
  Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier
 
 
Title: Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier
Author: Tan, Shou-biao
Lu, Wen-juan
Peng, Chun-yu
Li, Zheng-ping
Tao, You-wu
Chen, Jun-ning
Appeared in: Frontiers of information technology & electronic engineering
Paging: Volume 16 (2015) nr. 8 pages 700-706
Year: 2015
Contents:
Publisher: Zhejiang University Press, Hangzhou
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

                             Details for article 7 of 8 found articles
 
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