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Details for article 10 of 10 found articles
| Title: |
Synchronous Counters Implemented in the PLD Devices |
| Author: |
J. Kolouch |
| Appeared in: |
Radioengineering |
| Paging: | Volume 8 (1999) nr. 1 pages xx |
| Year: |
1999 |
| Contents: |
The implementability of synchronous counters in the Programmable Logic Devices (PLD) is discussed in this paper. The most commonly used counters are analysed from this point of view. The expressions for their individual bits are given and the number of product terms is derived to allow to estimate the size of the particular counter which can be implemented in the chosen PLD. |
| Publisher: |
Spolecnost pro radioelektronicke inzenyrstvi (provided by DOAJ) |
| Source file: |
Elektronische Wetenschappelijke Tijdschriften |
Details for article 10 of 10 found articles
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