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  System-Level Modeling of a Network-on-Chip
Titel: System-Level Modeling of a Network-on-Chip
Auteur: Ankur Agarwal
Verschenen in: International journal of computer science and security
Paginering: Jaargang 3 (2009) nr. 3 pagina's 154-174
Jaar: 2009
Inhoud: This paper presents the system-level modeling and simulation of a concurrent architecture for a customizable and scalable network-on-chip (NoC), using system level tools (MLDesigner). MLDesigner supports the integration of heterogeneous models of computation, which provide a framework to model various algorithms and activities, while accounting for and exploiting concurrency and synchronization aspects. Our methodology consists of three main phases: system-level concurrency modeling, component-level modeling, and system-level integration. At first, the Finite State Processes (FSP) symbolic language is used to model and analyze the system-level concurrency aspects of the NoC. Then, each component of the NoC is abstracted as a customizable class with parameters and methods, and instances of these classes are used to realize a 4×4 mesh-based NoC within the MLDesigner environment. To illustrate and validate the system-level operation of the NoC, we provide simulation results for various scheduling criteria, injection rates, buffer sizes, and network traffic patterns.
Uitgever: Computer Science Journals (provided by DOAJ)
Bronbestand: Elektronische Wetenschappelijke Tijdschriften

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