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| Titel: |
FPGA IMPLEMENTATION OF MAC HEADER BLOCK OF TRANSMITTER FOR Wi-Fi |
| Auteur: |
A.M.BHAVIKATTI, HAMEEDMIYAN, DHIRAJ DESHPANDE, L.M.DESHPANDE |
| Verschenen in: |
International journal of engineering science and technology |
| Paginering: | Jaargang 3 (2011) nr. 4 pagina's 3327-3335 |
| Jaar: |
2011 |
| Inhoud: |
For the wireless communication, IEEE 802.11 is one of the protocols available. The IEEE 802.11b uses the medium access control layer (MAC) for wireless local area network. These wireless local area networks use Carrier Sense multiple access with collision avoidance (CSMA/CS) for the MAC layer .But only the MAC layer for transmitter is considered here for simulation. So, the Wi-Fi transmitter module is divided into 5 blocks i.e. Data Unit Interface block, Controller block, Pay Load Data Storage, MAC Header Register block and Data Processing block. In this paper we consider only the simulation of MAC header register blocks. So, other blocks i.e. Data unit interface block, Controller block, pay load Data Storage block & Data Processing block are not discussed further in this paper. A field programmable gate array (FPGA) device has been used as the hardware implementation platform. The proposed MAC-layer hardware is implemented with Xilinx xcv300e Virtex E FPGA |
| Uitgever: |
Engg Journals Publication (provided by DOAJ) |
| Bronbestand: |
Elektronische Wetenschappelijke Tijdschriften |
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