Codificador y decodificador digital Reed-Solomon programados poara hardware reconfigurable
Titel:
Codificador y decodificador digital Reed-Solomon programados poara hardware reconfigurable
Auteur:
Cecilia E. Sandoval Ruiz Antonio Fedón
Verschenen in:
Ingeniería y Universidad
Paginering:
Jaargang 11 (2007) nr. 1 pagina's 17-31
Jaar:
2007
Inhoud:
In this paper we present theory bases for Reed-Solomon Coders/Decoders building blocks, and a methodology to the basic-oriented design of Field Programmable Gate Arrays (FPGA). Initially, the design of the Coder at the software level is presented, later the architecture and captures using VHDL, with Xilinx ISE 6.1 are showed. Finally, the simulations using ModelSim 5.7 are carried out. The operations in finite or Galois fields, GF(2m), are the fundamentals for several algorithms in the fields of error-correction codes and digital signal processing. Nevertheless, the calculations involved are time-consuming, especially when they are performed by software. Due to performance and security reasons, it is rather convenient to implement algorithms by hardware.
Uitgever:
Pontificia Universidad Javeriana, School of Engineering (provided by DOAJ)
Tijdschrift beschrijving