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Details for article 7 of 8 found articles
| Title: |
Proposal of synthesisable analogue-to-digital converters from VHDL-AMS |
| Author: |
Domenech-Asensi, G. Garrigos-Guerrero, J. |
| Appeared in: |
International journal of electronics |
| Paging: | Volume 95 (2008) nr. 9 pages 891-902 |
| Year: |
2008-09 |
| Contents: |
In this article, a procedure to describe synthesisable n-bits analogue-to-digital converters (ADC) using VHDL-AMS is presented. The aim is to propose specifications for reusable code generation which makes designers' tasks easier, shows clearly the underlying hardware structures, and is easily synthesisable by CAD-EDA tools. Two different architectures of ADC have been developed in order to show the guidelines for VHDL-AMS descriptions: a flash ADC and a serial ADC. Both descriptions meet the aforementioned conditions. In order to validate the synthesis methodology we have adapted a CAD-EDA tool specifically devoted to reconfigurable technology synthesis. We have synthesised a flash converter on a combination of FPGA and FPAA and the results have been measured in real devices. |
| Publisher: |
Taylor & Francis |
| Source file: |
Elektronische Wetenschappelijke Tijdschriften |
Details for article 7 of 8 found articles
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