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| Titel: |
High-speed CMOS demultiplexer with redundant multi-valued logic |
| Auteur: |
Kim, J. B. Ahn, S. H. |
| Verschenen in: |
International journal of electronics |
| Paginering: | Jaargang 94 (2007) nr. 10 pagina's 915-924 |
| Jaar: |
2007-10 |
| Inhoud: |
This paper describes an 11-Gb/s CMOS demultiplexer with redundant multi-valued logic. The proposed circuit receives serial binary data which is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the redundant multi-valued logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. The circuit is designed with a 0.35 µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The demultiplexer is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43 mW. This circuit is expected to operate at a higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency. |
| Uitgever: |
Taylor & Francis |
| Bronbestand: |
Elektronische Wetenschappelijke Tijdschriften |
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