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Details for article 3 of 9 found articles
| Title: |
A two-dimensional numerical model of a floating-gate EEPROM transistor |
| Author: |
Asquith, John Sung, Chang-Ling Ho, Fat Duen Chan, Chung Bun |
| Appeared in: |
International journal of electronics |
| Paging: | Volume 85 (1998) nr. 6 pages 697-712 |
| Year: |
1998-12-01 |
| Contents: |
A two-dimensional numerical model for an EEPROM transistor is developed using a finite difference method and Gummel's method (the decoupled method). A detailed procedure for developing this simulator is reported, which includes additional equations for handling specific boundaries and the effects of an EEPROM transistor. The current simulator is only concerned with FowlerNordheim tunnelling; it does not take the hot electron injection and band-toband tunnelling into account. The experimental data for NDTUN = 5 X 1019 cm-3 (NDTUN is the semiconductor surface dopant concentration under the tunnel oxide) verifies our model. For the erase operation this simulator is good for NDTUN > 1 X 1019 cm-3. For the write operation, however, it is good for all ranges of NDTUN. For the erase operation for NDTUN = 5 X 1018 cm-3, this simulator cannot get the abnormal peak current, but it yields a fair result if the high peak current is not considered. The importance of choosing the right values of Δt (the time step) is addressed. The CPU time (1 processor of Cray C90 computer) of the current simulator is about 24 min for Δt = 1 μs and Δt = 50 μs for the erase and write operations, respectively. |
| Publisher: |
Taylor & Francis |
| Source file: |
Elektronische Wetenschappelijke Tijdschriften |
Details for article 3 of 9 found articles
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