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Details van artikel 13 van 18 gevonden artikelen
| Titel: |
Novel concurrent architecture to implement the discrete cosine transform based on index partitions |
| Auteur: |
Wu, Ja-Ling Duh, Wei-Jou |
| Verschenen in: |
International journal of electronics |
| Paginering: | Jaargang 68 (1990) nr. 2 pagina's 165-174 |
| Jaar: |
1990-02-01 |
| Inhoud: |
In this paper a new concurrent architecture based on index partition and CORDIC techniques for implementing discrete cosine transforms (DCT) (with power of two length) is proposed. This architecture works basically in a serial-in parallel-out mode. In this newly proposed architecture, three stages of pipelining are applicable and the throughput rate is improved. Each processing element (PE) is basically a CORDIC processor with a fixed angle rotation and only N/2 PEs are required for computing an N-point DCT. Since each stage of the pipeline is nearly balanced, the concurrency of pipelining is explored as much as possible. The throughput rate of this architecture is (N + 2) / NT, where N is the transform length and T the system clock period. Therefore, in this architecture, the clock period can easily be pushed up to 50 ns in VLSI chips and the throughput rate would be 17-7 MHz for N = 16. Thus, this newly proposed architecture provides the posibility of real-time computations. |
| Uitgever: |
Taylor & Francis |
| Bronbestand: |
Elektronische Wetenschappelijke Tijdschriften |
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