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Details van artikel 13 van 18 gevonden artikelen
| Titel: |
Operation Simulation of an 8F21T2C-Type Ferroelectric Memory Array with a Revised Data Writing Method |
| Auteur: |
KIM, Hyun-Soo Yamamoto, Shuu'ichirou Ishiwara, Hiroshi |
| Verschenen in: |
Integrated ferroelectrics |
| Paginering: | Jaargang 56 (2003) nr. 1 pagina's 1045-1054 |
| Jaar: |
2003 |
| Inhoud: |
A planar 1T2C-type ferroelectric memory cell structure which has a unit cell area of 8F2 (F: minimum feature length) has been proposed. In this structure, the gate area, which is covered with a floating gate electrode, is 3F in length and F in width. Through the SPICE simulation for a 2 × 2 cell array, the basic operation for 8F2 1T2C-type memory cell was identified. Also, data disturbance problem during the data writing process in the 1T2C-type ferroelectric memory array was investigated using an equivalent capacitor model. Based on the analysis, a modified V/3 rule voltage application method for reducing the data disturbance effect was proposed and its validity was verified by SPICE simulation. |
| Uitgever: |
Taylor & Francis |
| Bronbestand: |
Elektronische Wetenschappelijke Tijdschriften |
Details van artikel 13 van 18 gevonden artikelen
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