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  A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture
 
 
Title: A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture
Author: Bhat, Kalpana G
Laxminidhi, T
Bhat, M S
Appeared in: S¯adhan¯a
Paging: Volume 44 (2019) nr. 6 pages 1-11
Year: 2019
Contents:
Publisher: Springer India, New Delhi
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

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